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CS43L21 数据表(PDF) 42 Page - Cirrus Logic |
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CS43L21 数据表(HTML) 42 Page - Cirrus Logic |
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42 / 63 page ![]() 42 DS723A1 CS43L21 Function: These bits select the gain multiplier for the headphone/line outputs. See “Line Output Voltage Characteris- tics” on page 14 and “Headphone Output Power Characteristics” on page 15. DAC Single Volume Control (DAC_SNGVOL) Default: 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control reg- isters when this function is disabled. When enabled, the volume on all channels is determined by the AOU- TA Volume Control register and the AOUTB Volume Control register is ignored. PCMX Invert Signal Polarity (INV_PCMX) Default: 0 0 - Disabled 1 - Enabled Function: When enabled, this bit will invert the signal polarity of the PCM x channel. DACX Channel Mute (DACX_MUTE) Default: 0 0 - Disabled 1 - Enabled Function: The output of channel x DAC will mute when enabled. The muting function is affected by the DACx Soft and Zero Cross bits (DACx_SZC[1:0]). 6.6 DAC Control (Address 09h) DAC Data Selection (DATA_SEL[1:0]) Default: 00 00 - PCM Serial Port to DAC 01 - Signal Processing Engine to DAC 10 - Reserved 11 - Reserved Function: Selects the digital signal source for the DAC. Note: Certain functions are only available when the “Signal Processing Engine to DAC” option is selected using these bits. 76 543 21 0 DATA_SEL1 DATA_SEL0 FREEZE Reserved DEEMPH AMUTE DAC_SZC1 DAC_SZC0 |
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