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CS43L21 数据表(PDF) 19 Page - Cirrus Logic

部件名 CS43L21
功能描述  Low Power, Stereo Digital to Analog Converter
PDF  63 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS43L21 数据表(HTML) 19 Page - Cirrus Logic

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DS723A1
19
CS43L21
SWITCHING CHARACTERISTICS - SPI™ CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL)
14. Data must be held for sufficient time to bridge the transition time of CCLK.
15. For fsck <1 MHz.
Parameter
Symbol
Min
Max
Units
CCLK Clock Frequency
fsck
06.0
MHz
RESET Rising Edge to CS Falling
tsrs
20
-
ns
CS Falling to CCLK Edge
tcss
20
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 14)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 15)
tr2
-100
ns
Fall Time of CCLK and CDIN
(Note 15)
tf2
-100
ns
CS
CCLK
CDIN
RST
t
srs
t
scl
t
sch
t
css
t
r2
t
f2
t
csh
t
dsu
t
dh
Figure 7. Control Port Timing - SPI Format



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