CS43L21 datasheet(32/63 Pages) CIRRUS

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DS723A1

CS43L21

4.8

Recommended Power-Down Sequence

To minimize audible pops when turning off or placing the D/A in standby,

Mute the DAC’s.

Set the PDN bit in the power control register to ‘1’b. The D/A will not power down until it reaches a fully

muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary to

disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down.

Bring RESET low.

Initialization

Software Mode

Registers setup to

desired settings.

RESET = Low?

No Power

1. No audio signal

generated.

Off Mode (Power Applied)

1. No audio signal generated.

2. Control Port Registers reset

to default.

Control Port

Active

Control Port Valid

Write Seq. within

10 ms?

Hardware Mode

Minimal feature

set support.

PDN bit = '1'b?

Sub-Clocks Applied

1. LRCK valid.

2. SCLK valid.

3. Audio samples

processed.

Valid

MCLK/LRCK

Ratio?

Yes

Normal Operation

Audio signal generated per control port or stand-

alone settings.

Analog Output Freeze

1. Aout bias = last audio sample.

2. DAC Modulators stop operation.

3. Audible pops.

ERROR: MCLK removed

PDN bit set to '1'b

(software mode only)

Standby Mode

1. No audio signal generated.

2. Control Port Registers retain

settings.

Reset Transition

1. Pops suppressed.

Power Off Transition

1. Audible pops.

ERROR: Power removed

Valid

MCLK Applied?

20 ms delay

Charge Caps

1. VQ Charged to

quiescent voltage.

2. Filtx+ Charged.

Digital/Analog

Output Muted

50 ms delay

Charge Pump

Powered Up

Headphone Amp

Powered Up

µs delay

Headphone Amp

Powered Down

µs delay

Stand-By

Transition

1. Pops suppressed.

ERROR: MCLK/LRCK ratio change

RESET = Low

Figure 17. Initialization Flow Chart

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