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CS43L21 数据表(PDF) 15 Page - Cirrus Logic |
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CS43L21 数据表(HTML) 15 Page - Cirrus Logic |
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15 / 63 page ![]() DS723A1 15 CS43L21 HEADPHONE OUTPUT POWER CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement band- width is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 16 Ω, CL = 10 pF (see Figure 3). 4. One-half LSB of triangular PDF dither is added to data. 5. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog Gain (HP_GAIN[2:0])” on page 41. High gain settings at certain VA and VA_HP supply levels may cause clipping when the audio signal approaches full-scale, maximum power output, as shown in Figures 21 - 24 on page 55. 6. See Figure 3. RL and CL reflect the recommended minimum resistance and maximum capacitance re- quired for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recom- mended 150 pF can cause the internal op-amp to become unstable. 7. VA_HP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC may not achieve the full THD+N performance at full-scale output voltage and power. Parameter VA = 2.5V (nominal) Min Typ Max VA = 1.8V (nominal) Min Typ Max Unit AOUTx Power Into RL = 16 Ω HP_GAIN[2:0] Analog Gain (G) VA_HP 000 0.3959 1.8 V - 14 - - 7 - mWrms 2.5 V - 14 - - 7 - mWrms 001 0.4571 1.8 V - 19 - - 10 - mWrms 2.5 V - 19 - - 10 - mWrms 010 0.5111 1.8 V - 23 - - 12 - mWrms 2.5 V - 23 - - 12 - mWrms 011 (default) 0.6047 1.8 V (Note 7) -17 - mWrms 2.5 V - 32 - - 17 - mWrms 100 0.7099 1.8 V (Note 7) -23 - mWrms 2.5 V - 44 - - 23 - mWrms 101 0.8399 1.8 V (Note 5) mWrms 2.5 V -32 - mWrms 110 1.0000 1.8 V (Note 5, 7) mWrms 2.5 V mWrms 111 1.1430 1.8 V mWrms 2.5 V mWrms AOUTx AGND R L C L 0.022 µF 51 Ω Figure 3. Headphone Output Test Load |
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