AT89C51CC02CA-RATUM datasheet(128/156 Pages) ATMEL

128 / 156 page

128

AT/T89C51CC02

4126J–CAN–05/06

The bits SCH0 to SCH2 in ADCON register are used for the analog input channel

selection.

Table 102. Selected Analog input

Voltage Conversion

When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If

the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between

VAREF and VAGND are a straight-line linear conversion. All other voltages will result in

3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN should not exceed VAREF absolute maximum range (See section

“AC-DC”).

Clock Selection

The ADC clock is the same as CPU.

The maximum clock frequency is defined in the DC parmeter for A/D converter. A pres-

caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.

if PRS = 0 then FADC = Fperiph / 64

if PRS > 0 then FADC = Fperiph / 2 x PRS

Figure 54. A/D Converter Clock

ADC Standby Mode

When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN

in ADCON register. In this mode the power dissipation is reduced.

SCH2

SCH1

SCH0

Selected Analog Input

000

AN0

001

AN1

010

AN2

011

AN3

100

AN4

101

AN5

110

AN6

111

AN7

Prescaler ADCLK

A/D

Converter

ADC Clock

CPU

CLOCK

CPU Core Clock Symbol

÷ 2

AT89C51CC02CA-RATUM 数据表(PDF) 128 Page - ATMEL Corporation

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