AT89C51CC02CA-RATUM datasheet(129/156 Pages) ATMEL

129 / 156 page

129

AT/T89C51CC02

4126J–CAN–05/06

IT ADC Management

An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit

EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software.

Figure 55. ADC interrupt structure

Routine Examples

1. Configure P1.2 and P1.3 in ADC channels

// configure channel P1.2 and P1.3 for ADC

ADCF = 0Ch

// Enable the ADC

ADCON = 20h

2. Start a standard conversion

// The variable ’channel’ contains the channel to convert

// The variable ’value_converted’ is an unsigned int

// Clear the field SCH[2:0]

ADCON &= F8h

// Select channel

ADCON |= channel

// Start conversion in standard mode

ADCON |= 08h

// Wait flag End of conversion

while((ADCON & 01h)!= 01h)

// Clear the End of conversion flag

ADCON &= EFh

// read the value

value_converted = (ADDH << 2)+(ADDL)

3. Start a precision conversion (need interrupt ADC)

// The variable ’channel’ contains the channel to convert

// Enable ADC

EADC = 1

// clear the field SCH[2:0]

ADCON &= F8h

// Select the channel

ADCON |= channel

// Start conversion in precision mode

ADCON |= 48h

Note:

To enable the ADC interrupt: EA = 1

ADEOC

ADCON.2

EADC

IEN1.1

ADCI

AT89C51CC02CA-RATUM 数据表(PDF) 129 Page - ATMEL Corporation

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