AT89C51CC02CA-RATUM datasheet(130/156 Pages) ATMEL

130 / 156 page

130

AT/T89C51CC02

4126J–CAN–05/06

Registers

Table 103. ADCF Register

ADCF (S:F6h)

ADC Configuration

Reset Value = 0000 0000b

Table 104. ADCON Register

ADCON (S:F3h)

ADC Control Register

Reset Value = X000 0000b

CH 7

CH 6

CH 5

CH 4

CH 3

CH 2

CH 1

CH 0

Bit

Number

Bit

Mnemonic

Description

7 - 0

CH 0:7

Channel Configuration

Set to use P1.x as ADC input.

Clear to use P1.x as standart I/O port.

PSIDLE

ADEN

ADEOC

ADSST

SCH2

SCH1

SCH0

Bit

Number

Bit

Mnemonic

Description

Reserved

The value read from these bits are indeterminate. Do not set these bits.

PSIDLE

Pseudo Idle Mode (Best Precision)

Set to put in idle mode during conversion

Clear to convert without idle mode.

5ADEN

Enable/Standby Mode

Set to enable ADC

Clear for Standby mode.

4ADEOC

End Of Conversion

Set by hardware when ADC result is ready to be read. This flag can generate an

interrupt.

Must be cleared by software.

ADSST

Start and Status

Set to start an A/D conversion.

Cleared by hardware after completion of the conversion

2-0

SCH2:0

Selection of Channel to Convert

See Table 102

AT89C51CC02CA-RATUM 数据表(PDF) 130 Page - ATMEL Corporation

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