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AM29BDD160G 数据表(PDF) 21 Page - Advanced Micro Devices

部件名 AM29BDD160G
功能描述  16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
PDF  79 Pages
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

AM29BDD160G 数据表(HTML) 21 Page - Advanced Micro Devices

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June 7, 2006
Am29BDD160G
19
enabled using a 16-bit DQ bus (WORD# = V
IL), the
IND/WAIT# signal transitions active on the fourth ac-
cess. If the same scenario is used, but instead the
32-bit DQ bus is enabled, the IND/WAIT# signal transi-
tions active on the second access. The IND/WAIT#
signal has the same delay and setup timing as the DQ
pins. Also, the IND/WAIT# signal is controlled by the
OE# signal. If OE# is at V
IH, the IND/WAIT# signal
floats and is not driven. If OE# is at V
IL, the IND/WAIT#
signal is driven at V
IH until it transitions to VIL indicating
the end of burst sequence. The IND/WAIT# signal tim-
ing and duration is (See “Configuration Register” for
more information). The following table lists the valid
combinations of the Configuration Register bits that
impact the IND/WAIT# timing.



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