AM29BDD160G datasheet(24/79 Pages) AMD

24 / 79 page

Am29BDD160G

June 7, 2006

Burst CLK Edge Data Delivery

The Am29BDD160 is capable of delivering data on ei-

ther the rising or falling edge of CLK. To deliver data

on the rising edge of CLK, bit 6 in the Control Register

(CR6) is set to 1. To deliver data on the falling edge of

CLK, bit 6 in the Control Register is cleared to 0. The

default configuration is set to the rising edge.

Burst Data Hold Control

The device is capable of holding data for one CLKs.

The default configuration is to hold data for one CLK

and is the only valid state.

Asserting RESET# During A Burst Access

If RESET# is asserted low during a burst access, the

burst access is immediately terminated and the device

defaults back to asynchronous read mode. Refer to

RESET#: Hardware Reset Pin for more information on

the RESET# function.

Configuration Register

The Am29BDD160 contains a Configuration Register

for configuring read accesses. The Configuration Reg-

ister is accessed by the Configuration Register Read

and the Configuration Register Write commands. The

Configuration Register does not occupy any address-

able memory location, but rather, is accessed by the

Configuration Register commands. The Configuration

Configuration Register is restricted to times when the

Embedded Algorithm™ is not active. If the user at-

tempts to write the Configuration Register while the

Embedded Algorithm™ is active, the write operation is

ignored and the contents of the Configuration Register

remain unchanged.

The Configuration Register is a 16 bit data field which

is accessed by DQ15–DQ0. Data on DQ31–DQ16 is

ignored during a write operation when WORD# = V

IL.

During a read operation, DQ31–DQ16 returns all ze-

roes. Table 9 shows the Configuration Register. Also,

Configuration Register reads operate the same as Au-

toselect command reads. When the command is is-

sued, the bank address is latched along with the

command. Reads operations to the bank that was

specified during the Configuration Register read com-

mand return Configuration Register contents. Read

operations to the other bank return flash memory data.

Either bank address is permitted when writing the

Configuration Register read command.

Table 9.

Configuration Register Definitions

CR15

CR14

CR13

CR12

CR11

CR10

CR9

CR8

Reserved

IAD3

IAD2

IAD1

IAD0

DOC

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

Reserved

BL2

BL1

BL0

Configuration Register

CR15 = Read Mode (RM)

0 = Synchronous Burst Reads Enabled

1 = Asynchronous Reads Enabled (Default)

CR14 = Reserved for Future Enhancements

These bits are reserved for future use. Set these bits to “0”.

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