AM29BDD160G datasheet(47/79 Pages) AMD

47 / 79 page

June 7, 2006

Am29BDD160G

Legend:

BA = Address of the bank that is being switched to autoselect mode,

is in bypass mode, or is being erased. Determined by A18 and A17,

see Tables 11 and 12 for more detail.

PA = Program Address (A18:A0). Addresses latch on the falling edge

of the WE# or CE# pulse, whichever happens later.

PD = Program Data (DQ31:DQ0) written to location PA. Data latches

on the rising edge of WE# or CE# pulse, whichever happens first.

RA = Read Address (A18:A0).

RD = Read Data (DQ31:DQ0) from location RA.

SA = Sector Address (A18:A11) for verifying (in autoselect mode),

erasing, or applying security commands.

WD = Write Data. See “Configuration Register” definition for specific

write data. Data latched on rising edge of WE#.

X = Don’t care

Notes:

See Table 1 for description of bus operations.

All values are in hexadecimal.

Shaded cells in table denote read cycles. All other cycles are

write operations.

During unlock cycles, (lower address bits are 555 or 2AAh as

shown in table) address bits higher than A11 (except where BA is

required) and data bits higher than DQ7 are don’t cares.

No unlock or command cycles required when bank is reading

array data.

The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when a bank is in the autoselect mode, or if DQ5 goes high (while

the bank is providing status information).

The fourth cycle of the autoselect command sequence is a read

cycle. The system must provide the bank address to obtain the

manufacturer ID or device ID information. See the Autoselect

Command section for more information.

This command cannot be executed until The Unlock Bypass

command must be executed before writing this command

sequence. The Unlock Bypass Reset command must be

executed to return to normal operation.

This command is ignored during any embedded program, erase

or suspended operation.

10. Valid read operations include asynchronous and burst read mode

operations.

11. The device ID must be read across the fourth, fifth, and sixth

cycles. 00h in the sixth cycle indicates top boot block, 01h

indicates bottom boot block.

12. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Program/Erase Suspend

mode. The Program/Erase Suspend command is valid only

during a sector erase operation, and requires the bank address.

13. The Program/Erase Resume command is valid only during the

Erase Suspend mode, and requires the bank address.

14. Command is valid when device is ready to read array data or

when device is in autoselect mode.

15. Asynchronous read operations.

16. ACC must be at V

ID during the entire operation of this command.

17. Command is ignored during any Embedded Program, Embedded

Erase, or Suspend operation.

18. The Unlock Bypass Entry command is required prior to any

Unlock Bypass operation. The Unlock Bypass Reset command is

required to return to the read mode.

Table 19.

Memory Array Command Definitions (x32 Mode)

Command (Notes)

Bus Cycles (Notes 1–4)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read (5)

Reset (6)

XXX

Autoselect

(7)

Manufacturer ID

555

2AA

555

(BA)X00

Device ID (11)

555

2AA

555

(BA)X01

(BA)X0E

(BA)X0F 00/01

Program

555

2AA

555

Chip Erase

555

2AA

555

2AA

555

Sector Erase

555

2AA

555

2AA

Program/Erase Suspend (12)

Program/Erase Resume (13)1

CFI Query (14, 15)

Accelerated Program (16)

Configuration Register Verify (15)

555

2AA

(BA)555

(BA)XX

Configuration Register Write (17)

555

2AA

555

Unlock Bypass Entry (18)

555

2AA

555

Unlock Bypass Program (18)

Unlock Bypass Erase (18)2

80XX

Unlock Bypass CFI (14, 18)1

Unlock Bypass Reset (18)2

90XX

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