AM29BDD160G datasheet(25/79 Pages) AMD

25 / 79 page

June 7, 2006

Am29BDD160G

CR13–CR10 = Initial Burst Access Delay Configuration (IAD3-IAD0)

Speed Options 54D, 64C, 65A:

0000 = 2 CLK cycle initial burst access delay

0001 = 3 CLK cycle initial burst access delay

0010 = 4 CLK cycle initial burst access delay

0011 = 5 CLK cycle initial burst access delay

0100 = 6 CLK cycle initial burst access delay

0101 = 7 CLK cycle initial burst access delay

0110 = 8 CLK cycle initial burst access delay

0111 = 9 CLK cycle initial burst access delay—Default

CR9 = Data Output Configuration (DOC)

0 = Hold Data for 1-CLK cycle—Default

1 = Reserved

CR8 = IND/WAIT# Configuration (WC)

0 = IND/WAIT# Asserted During Delay—Default

1 = IND/WAIT# Asserted One Data Cycle Before Delay

CR7 = Burst Sequence (BS)

0 = Reserved

1 = Linear Burst Order—Default

CR6 = Clock Configuration (CC)

0 = Reserved

1 = Burst Starts and Data Output on Rising Clock Edge—Default

CR5–CR3 = Reserved For Future Enhancements (R)

These bits are reserved for future use. Set these bits to “0.”

CR2–CR0 = Burst Length (BL2–BL0)

000 = Reserved, burst accesses disabled (asynchronous reads only)

001 = 64 bit (8-byte) Burst Data Transfer - x16 and x32 Linear

010 = 128 bit (16-byte) Burst Data Transfer - x16 and x32 Linear

011 = 256 bit (32-byte) Burst Data Transfer - x16 Linear Only and x32 Linear

100 = 512 bit (64-byte) Burst Data Transfer - x16 Linear Only - Default

101 = Reserved, burst accesses disabled (asynchronous reads only)

110 = Reserved, burst accesses disabled (asynchronous reads only)

111 = Reserved

Table 9.

Configuration Register Definitions (Continued)

AM29BDD160G 数据表(PDF) 25 Page - Advanced Micro Devices

AM29BDD160G 数据表(HTML) 25 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

数据表下载