AM29BDD160G datasheet(37/79 Pages) AMD

37 / 79 page

June 7, 2006

Am29BDD160G

The Reset command does not disable the SecSi sec-

tor if it is enabled. This function is only accomplished

by issuing the SecSi Sector Exit command.

Autoselect Command

Flash memories are intended for use in applications

where the local CPU alters memory contents. As such,

manufacturer and device codes must be accessible

while the device resides in the target system. PROM

programmers typically access the signature codes by

raising A9 to V

ID. However, multiplexing high voltage

onto the address lines is not generally desired system

design practice.

The Am29BDD160 contains an Autoselect Command

operation to supplement traditional PROM program-

ming methodology. The operation is initiated by writing

the Autoselect command sequence into the command

autoselect command sequence write operation to dis-

tinguish which bank the Autoselect command refer-

ences. Reading the other bank after the Autoselect

command is written results in reading array data from

the other bank and the specified address. Following

the command write, a read cycle from address

(BA)XX00h retrieves the manufacturer code of

(BA)XX01h. Three sequential read cycles at ad-

dresses (BA) XX01h, (BA) XX0Eh, and (BA) XX0Fh

read the three-byte device ID (see Tables 19 and 20).

All manufacturer and device codes exhibit odd parity

with the MSB of the lower byte (DQ7) defined as the

parity bit.

(The Autoselect Command requires the user to exe-

cute the Read/Reset command to return the device

back to reading the array contents.)

Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically gener-

ates the program pulses and verifies the programmed

cell margin. Tables 18 and 20 shows the address and

data requirements for the program command se-

quence.

During the Embedded Program algorithm, the system

can determine the status of the program operation by

using DQ7, DQ6, or RY/BY#. (See Write Operation

Status for information on these status bits.) When the

Embedded Program algorithm is complete, the device

returns to reading array data and addresses are no

longer latched. Note that an address change is re-

quired to begin read valid array data.

Except for Program Suspend, any commands written

to the device during the Embedded Program Algorithm

are ignored. Note that a hardware reset immediately

terminates the programming operation. The command

sequence should be reinitiated once that bank has re-

turned to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may

halt the operation and set DQ5 to “1,” or cause the

Data# Polling algorithm to indicate the operation was

successful. However, a succeeding read will show that

the data is still “0”. Only erase operations can convert

a “0” to a “1”.

Accelerated Program Command

The Accelerated Chip Program mode is designed to

improve the Word or Double Word programming

speed. Improving the programming speed is accom-

plished by using the ACC pin to supply both the word-

line voltage and the bitline current instead of using the

PP pump and drain pump, which is limited to 2.5 mA.

Because the external ACC pin is capable of supplying

significantly large amounts of current compared to the

drain pump, all 32 bits are available for programming

with a single programming pulse. This is an enormous

improvement over the standard 5-bit programming. If

the user is able to supply an external power supply

and connect it to the ACC pin, significant time savings

are realized.

In order to enter the Accelerated Program mode, the

ACC pin must first be taken to V

HH (12 V ± 0.5 V) and

followed by the one-cycle command with the program

address and data to follow. The Accelerated Chip Pro-

gram command is only executed when the device is in

Unlock Bypass mode and during normal read/reset

operating mode.

In this mode, the write protection function is bypassed

unless the PPB Lock Bit = 1.

The Accelerated Program command is not permitted if

the SecSi sector is enabled.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram words to the device faster than using the stan-

dard program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is followed by a third write cycle con-

taining the unlock bypass command, 20h. The device

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program

address and data. Additional data is programmed in

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