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AM29BDD160G 数据表(PDF) 50 Page - Advanced Micro Devices

部件名 AM29BDD160G
功能描述  16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
PDF  79 Pages
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

AM29BDD160G 数据表(HTML) 50 Page - Advanced Micro Devices

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Am29BDD160G
June 7, 2006
Legend:
DYB = Dynamic Protection Bit
OW = Address (A5–A0) is (011X10).
PD3:0 = Four 32-bit quantities representing the password.
PPB = Persistent Protection Bit
PWA = Password Address. A0:A-1 selects between the low and high
16-bit portions of the 64-bit Password
PWD = Password Data.Must be written over four cycles.
PL = Password Protection Mode Lock Address (A5-A0) is (001X10)
RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0 =
1, if unprotected, DQ0 = 0.
RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 =
1, if unprotected, DQ1 = 0.
SA = Sector Address where security command applies. Address bits
A18:A11 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10)
WP = PPB Address (A5–A0) is (111X10)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
1.
See Table 1 for description of bus operations.
2.
All values are in hexadecimal.
3.
Shaded cells in table denote read cycles. All other cycles are
write operations.
4.
During unlock cycles, (lower address bits are AAA or 555h as
shown in table) address bits higher than A11 (except where BA is
required) and data bits higher than DQ7 are don’t cares.
5.
The reset command returns the device to reading the array.
6.
The fourth cycle programs the addressed locking bit. The fifth and
sixth cycles are used to validate whether the bit has been fully
programmed. If DQ0 (in the sixth cycle) reads 0, the program
command must be issued and verified again.
7.
Data is latched on the rising edge of WE#.
8.
The entire four bus-cycle sequence must be entered for each
portion of the password. PWA[0–3] represent the four addresses
over which the password is stored. PWD[0–3] represent the four
word data that comprise the password.
9.
The fourth cycle erases all PPBs. The fifth and sixth cycles are
used to validate whether the bits have been fully erased. If DQ0
(in the sixth cycle) reads 1, the erase command must be issued
and verified again.
10. Before issuing the erase command, all PPBs should be
programmed in order to prevent over-erasure of PPBs.
11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not
set.
12. The status of additional PPBs and DYBs may be read (following
the fourth cycle) without reissuing the entire command sequence.
Table 22.Sector Protection Command Definitions (x16 Mode)
Command (Notes)
Bus Cycles (Notes 1-4)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Reset
1
XXX
F0
SecSi Sector Entry
3
AAA
AA
555
55
AAA
88
SecSi Sector Exit
4
AAA
AA
555
55
AAA
90XX
00
SecSi Protection Bit Program
(5, 6)
6
AAA
AA
555
55
AAA
60
OW
68
OW
48
OW
RD(0)
SecSi Protection Bit Status
6
AAA
AA
555
55
AAA
60
OW
RD(0)
Password Program (5, 7, 8)
5
AAA
AA
555
55
AAA
38
PWA[0–3] PWD[0–3]
Password Verify
4
AAA
AA
555
55
AAA
C8
PWA[0–3] PWD[0–3]
Password Unlock (7, 8)
5
AAA
AA
555
55
AAA
28
PWA[0–3] PWD[0–3]
PPB Program (5, 6)
6
AAA
AA
555
55
AAA
60
(SA)WP
68
(SA)WP
48
(SA)WP RD(0)
All PPB Erase (5, 9, 10)
6
AAA
AA
555
55
AAA
60
WP
60
(SA)WP
40
(SA)WP RD(0)
PPB Status (11, 12)
4
AAA
AA
555
55
AAA
90(SA)X04
00/01
PPB Lock Bit Set
3
AAA
AA
555
55
AAA
78
PPB Lock Bit Status
4
AAA
AA
555
55
(BA) AAA
58
SA
RD(1)
DYB Write (7)
4
AAA
AA
555
55
AAA
48SAX1
DYB Erase (7)
4
AAA
AA
555
55
AAA
48SAX0
DYB Status (12)
4
AAA
AA
555
55
(BA) AAA
58
SA
RD(0)
PPMLB Program (5, 6)
6
AAA
AA
555
55
AAA
60
PL
68
PL
48
PL
RD(0)
PPMLB Status (5)
6
AAA
AA
555
55
AAA
60
PL
RD(0)
SPMLB Program (5, 6)
6
AAA
AA
555
55
AAA
60
SL68SL48
SL
RD(0)
SPMLB Status (5)
6
AAA
AA
555
55
AAA
60
SL
RD(0)



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