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数据搜索系统，热门电子元器件搜索 |
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AM29BDD160G 数据表(PDF) 61 Page - Advanced Micro Devices |
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AM29BDD160G 数据表(HTML) 61 Page - Advanced Micro Devices |
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61 / 79 page  June 7, 2006 Am29BDD160G 59 AC CHARACTERISTICS Burst Mode Read Note: See Product Selector Guide for minimum initial clock delay prior to initial valid data. t IACC may also be calculated using the following formula: t IACC = (clock delays) x (clock period) + tBACC. Parameter Description Speed Options Unit JEDEC Std. 54D 64C 65A t IACC Asynchronous Access Time ADV# Valid Clock to Output Delay (See Note) Max 54 64 67 ns t BACC Burst Access Time Valid Clock to Output Delay Max 9 FBGA 9.5 PQFP 10 FBGA 10 PQFP 17 ns t ADVCS ADV# Setup Time to Rising (Falling) Edge of CLK Min 4 5 7 ns t ADVCH ADV# Hold Time Min 2 ns t ADVP ADV# Pulse Width Min 15 15 18 ns t BDH Data Hold Time from Next Clock Cycle Max 4 ns t DVCH Valid Data Hold from CLK Min 2 3 3 ns t DIND CLK to Valid IND/WAIT# Max 9 FBGA 9.5 PQFP 10 FBGA 10 PQFP 17 ns t INDH IND/WAIT# Hold from CLK Min 2 3 3 ns t IACC CLK to Valid Data Out, Initial Burst Access Max 54 60 68 ns t CLK CLK Period Min 15 18 25 ns Max 60 t CR CLK Rise Time Max 3 ns t CF CLK Fall Time Max 3 ns t CH CLK High Time Min 2.5 2.5 3 ns t CL CLK Low Time Min 2.5 2.5 3 ns t CH CE# Hold Time Min 3 ns t ACS Address Setup Time to CLK (See Note) Min 5 6 7 ns t ACH Address Hold Time from ADV# Rising Edge (See Note) Min 1 2 2 ns t OE Output Enable to Output Valid Max 20 ns t DF t OEZ Output Enable to Output High Z Min 2 3 3 ns Max 10 15 17 t EHQZ t CEZ Chip Enable to Output High Z Max 10 15 17 ns t CES CE# Setup Time to Clock Min 4 5 6 ns |
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