AM29BDD160G datasheet(48/79 Pages) AMD

48 / 79 page

Am29BDD160G

June 7, 2006

DYB = Dynamic Protection Bit

OW = Address (A5–A0) is (011X10).

PPB = Persistent Protection Bit

PWA = Password Address. A0 selects between the low and high

32-bit portions of the 64-bit Password

PWD = Password Data. Must be written over two cycles.

PL = Password Protection Mode Lock Address (A5–A0) is (001X10)

RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0= 1,

if unprotected, DQ0 = 0.

RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 =

1, if unprotected, DQ1 = 0.

SA = Sector Address where security command applies. Address bits

A18:A11 uniquely select any sector.

SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10)

WP = PPB Address (A5–A0) is (111X10)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

See Table 1 for description of bus operations.

All values are in hexadecimal.

Shaded cells in table denote read cycles. All other cycles are

write operations.

During unlock cycles, (lower address bits are 555 or 2AAh as

shown in table) address bits higher than A11 (except where BA is

required) and data bits higher than DQ7 are don’t cares.

The reset command returns the device to reading the array.

The fourth cycle programs the addressed locking bit. The fifth and

sixth cycles are used to validate whether the bit has been fully

programmed. If DQ0 (in the sixth cycle) reads 0, the program

command must be issued and verified again.

Data is latched on the rising edge of WE#.

The entire four bus-cycle sequence must be entered for each

portion of the password.

The fourth cycle erases all PPBs. The fifth and sixth cycles are

used to validate whether the bits have been fully erased. If DQ0

(in the sixth cycle) reads 1, the erase command must be issued

and verified again.

10. Before issuing the erase command, all PPBs should be

programmed in order to prevent over-erasure of PPBs.

11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not

set.

12. The status of additional PPBs and DYBs may be read (following

the fourth cycle) without reissuing the entire command sequence.

Table 20.Sector Protection Command Definitions (x32 Mode)

Command (Notes)

Bus Cycles (Notes 1-4)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Reset

XXX

SecSi Sector Entry

555

2AA

555

SecSi Sector Exit

555

2AA

555

90XX

SecSi Protection Bit Program (5, 6)

555

2AA

555

RD(0)

SecSi Protection Bit Status

555

2AA

555

RD(0)

Password Program (5, 7, 8)

555

2AA

555

PWA[0-1] PWD[0-1]

Password Verify

555

2AA

555

PWA[0-1] PWD[0-1]

Password Unlock (7, 8)

555

2AA

555

PWA[0-1] PWD[0-1]

PPB Program (5, 6)

555

2AA

555

(SA)WP

(SA)WP RD(0)

All PPB Erase (5, 9, 10)

555

2AA

555

(SA)WP

(SA)WP RD(0)

PPB Status (11, 12)

555

2AA

555

90(SA)X02

00/01

PPB Lock Bit Set

555

2AA

555

PPB Lock Bit Status

555

2AA

(BA) 555

RD(1)

DYB Write (7)

555

2AA

555

48SAX1

DYB Erase (7)

555

2AA

555

48SAX0

DYB Status (12)

555

2AA

(BA) 555

RD(0)

PPMLB Program (5,6)

555

2AA

555

RD(0)

PPMLB Status (5)

555

2AA

555

RD(0)

SPMLB Program (5, 6)

555

2AA

555

SL68SL48

RD(0)

SPMLB Status (5)

555

2AA

555

RD(0)

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