AM29BDD160G datasheet(51/79 Pages) AMD

51 / 79 page

June 7, 2006

Am29BDD160G

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,

and RY/BY#. Table 23 and the following subsections

describe the functions of these bits. DQ7, RY/BY#, and

DQ6 each offer a method for determining whether a

program or erase operation is complete or in progress.

These three bits are discussed first.

DQ7: Data# Polling

The Am29BDD160 features a Data# polling flag as a

method to indicate to the host system whether the em-

bedded algorithms are in progress or are complete.

During the Embedded Program Algorithm an attempt

to read the bank in which programming was initiated

will produce the complement of the data last written to

DQ7. Upon completion of the Embedded Program Al-

gorithm, an attempt to read the device will produce the

true last data written to DQ7. Note that DATA# polling

returns invalid data for the address being programmed

or erased.

For example, the data read for an address pro-

grammed as 0000 0000 1000 0000b will return XXXX

XXXX 0XXX XXXXb during an Embedded Program

operation. Once the Embedded Program Algorithm is

complete, the true data is read back on DQ7. Note that

at the instant when DQ7 switches to true data, the

other bits may not yet be true. However, they will all be

true data on the next read from the device. Please

note that Data# polling may give misleading status

when an attempt is made to write to a protected sec-

tor.

For chip erase, the Data# polling flag is valid after the

rising edge of the sixth WE# pulse in the six write

pulse sequence. For sector erase, the Data# polling is

valid after the last rising edge of the sector erase WE#

pulse. Data# polling must be performed at sector ad-

dresses within any of the sectors being erased and not

a sector that is a protected sector. Otherwise, the sta-

tus may not be valid. DQ7 = 0 during an Embedded

Erase Algorithm (chip erase or sector erase operation)

but will return a “1” after the operation completes be-

cause it will have dropped back into read mode.

In asynchronous mode, just prior to the completion of

the Embedded Algorithm operations, DQ7 may

change asynchronously while OE# is asserted low. (In

synchronous mode, ADV# exhibits this behavior.) The

status information may be invalid during the instance

of transition from status information to array (memory)

data. An extra validity check is therefore specified in

the data polling algorithm. The valid array data on

DQ31–DQ0 (DQ15–DQ0 when WORD# = 0) is avail-

able for reading on the next successive read attempt.

The Data# polling feature is only active during the Em-

bedded Programming Algorithm, Embedded Erase Al-

gorithm, Erase Suspend, Erase Suspend-Program

mode, or sector erase time-out.

If the user attempts to write to a protected sector,

Data# polling will be activated for about 1 µs: the de-

vice will then return to read mode, with the data from

the protected sector unchanged. If the user attempts

to erase a protected sector, Toggle Bit (DQ6) will be

activated for about 150 µs; the device will then return

to read mode, without having erased the protected

sector.

Table 23 shows the outputs for Data# Polling on DQ7.

Figure 6 shows the Data# Polling algorithm. Figure 27

shows the timing diagram for synchronous status DQ7

data polling.

RY/BY#: Ready/Busy#

The device provides a RY/BY# open drain output pin as

a way to indicate to the host system that the Embedded

Algorithms are either in progress or have been com-

pleted. If the output is low, the device is busy with either

a program, erase, or reset operation. If the output is

floating, the device is ready to accept any read/write or

erase operation. When the RY/BY# pin is low, the de-

vice will not accept any additional program or erase

commands with the exception of the Erase suspend

command. If the device has entered Erase Suspend

mode, the RY/BY# output will be floating. For program-

ming, the RY/BY# is valid (RY/BY# = 0) after the rising

edge of the fourth WE# pulse in the four write pulse se-

quence. For chip erase, the RY/BY# is valid after the

rising edge of the sixth WE# pulse in the six write pulse

sequence. For sector erase, the RY/BY# is also valid

after the rising edge of the sixth WE# pulse.

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the in-

ternal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether the

reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “floating”), the reset operation is com-

pleted in a time of tREADY (not during Embedded Algo-

rithms). The system can read data tRH after the

RESET# pin returns to VIH.

Since the RY/BY# pin is an open-drain output, several

RY/BY# pins can be tied together in parallel with a

pull-up resistor to VCC. An external pull-up resistor is re-

quired to take RY/BY# to a VIH level since the output is

an open drain.

Table 23 shows the outputs for RY/BY#. Figures 15, 19,

21 and 22 shows RY/BY# for read, reset, program, and

erase operations, respectively.

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