AM29BDD160G datasheet(36/79 Pages) AMD

36 / 79 page

Am29BDD160G

June 7, 2006

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Tables 18-21 define the valid register

command sequences. Writing incorrect address and

data values or writing them in the improper se-

quence resets the device to reading array data.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the AC Characteristics section for timing

diagrams.

Reading Array Data in Non-burst Mode

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

After the device accepts an Erase Suspend com-

mand, the device enters the Erase Suspend mode.

The system can read array data using the standard

read timings, except that if it reads at an address

within erase-suspended sectors, the device outputs

status data. After completing a programming opera-

tion in the Erase Suspend mode, the system may

once again read array data with the same exception.

See Sector Erase and Program Suspend Command

for more information on this mode.

The system must issue the reset command to re-en-

able the device for reading array data if DQ5 goes high,

or while in the autoselect mode. See the The program-

ming of the PPB Lock Bit for a given sector can be ver-

ified by writing a PPB Lock Bit status verify command

to the device. section.

See also Asynchronous Read Operation (Non-Burst) in

the Key to Switching Waveforms section for more

information. See the Sector Erase and Program Resume

Command sections for more information on this mode.

Reading Array Data in Burst Mode

The device is capable of very fast Burst mode read op-

erations. The configuration register sets the read con-

figuration, burst order, frequency configuration, and

burst length.

Upon power on, the device defaults to the asynchro-

nous mode. In this mode, CLK, and ADV# are ignored.

The device operates like a conventional Flash device.

Data is available t

ACC/tCE nanoseconds after address

becomes stable, CE# become asserted. The device

enters the burst mode by enabling synchronous burst

reads in the configuration register. The device exits

burst mode by disabling synchronous burst reads in

the configuration register. (See Command Definitions).

The RESET# command will not terminate the Burst

mode. System reset (power on reset) will terminate

the Burst mode.

The device has the regular control pins, i.e. Chip En-

able (CE#), Write Enable (WE#), and Output Enable

(OE#) to control normal read and write operations.

Moreover, three additional control pins have been

added to allow easy interface with minimal glue logic

to a wide range of microprocessors / microcontrollers

for high performance Burst read capability. These ad-

ditional pins are Address Valid (ADV#) and Clock

(CLK). CE#, OE#, and WE# are asynchronous (rela-

tive to CLK). The Burst mode read operation is a syn-

chronous operation tied to the edge of the clock. The

microprocessor / microcontroller supplies only the ini-

tial address, all subsequent addresses are automati-

cally generated by the device with a timing defined by

the Configuration Register definition. The Burst read

cycle consists of an address phase and a correspond-

ing data phase.

During the address phase, the Address Valid (ADV#)

pin is asserted (taken Low) for one clock period. To-

gether with the edge of the CLK, the starting burst ad-

dress is loaded into the internal Burst Address

Counter. The internal Burst Address Counter can be

configured to either the Linear modes (See “Initial Ac-

cess Delay Configuration”).

During the data phase, the first burst data is available

after the initial access time delay defined in the Config-

uration Register. For subsequent burst data, every ris-

ing (or falling) edge of the CLK will trigger the output

data with the burst output delay and sequence defined

in the Configuration Register.

Tables 17–20 show all the commands executed by the

device. The device automatically powers up in the

read/reset state. It is not necessary to issue a read/re-

set command after power-up or hardware reset.

Read/Reset Command

After power-up or hardware reset, the Am29BDD160

automatically enter the read state. It is not necessary

to issue the reset command after power-up or hard-

ware reset. Standard microprocessor cycles retrieve

array data, however, after power-up, only asynchro-

nous accesses are permitted since the Configuration

abled.

The Reset command is executed when the user needs

to exit any of the other user command sequences

(such as autoselect, program, chip erase, etc.) to re-

turn to reading array data. There is no latency be-

tween executing the Reset command and reading

array data.

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