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MPC8540CPX667JC 数据表(PDF) 48 Page - Freescale Semiconductor, Inc |
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MPC8540CPX667JC 数据表(HTML) 48 Page - Freescale Semiconductor, Inc |
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48 / 104 page  MPC8540 Integrated Processor Hardware Specifications, Rev. 4 48 Freescale Semiconductor I2C Figure 28 provides the test access port timing diagram. Figure 28. Test Access Port Timing Diagram 11 I2C This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8540. 11.1 I2C DC Electrical Characteristics Table 39 provides the DC electrical characteristics for the I2C interface of the MPC8540. Table 39. I2C DC Electrical Characteristics At recommended operating conditions with OVDD of 3.3 V ± 5%. Parameter Symbol Min Max Unit Notes Input high voltage level VIH 0.7 × OV DD OVDD+ 0.3 V Input low voltage level VIL –0.3 0.3 × OV DD V Low level output voltage VOL 00.2 × OV DD V1 Pulse width of spikes which must be suppressed by the input filter tI2KHKL 050 ns 2 Input current each I/O pin (input voltage is between 0.1 × OV DD and 0.9 × OVDD(max) II –10 10 μA3 Capacitance for each I/O pin CI —10 pF Notes: 1.Output voltage (open drain or open collector) condition = 3 mA sink current. 2.Refer to the MPC8540 Integrated Processor Preliminary Reference Manual for information on the digital filter used. 3.I/O pins will obstruct the SDA and SCL lines if OVDD is switched off. VM = Midpoint Voltage (OVDD/2) VM VM tJTIVKH tJTIXKH JTAG External Clock Output Data Valid tJTKLOX tJTKLOZ tJTKLOV Input Data Valid Output Data Valid TDI, TMS TDO TDO |
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