MPC8540CPX667JC datasheet(49/104 Pages) FREESCALE

49 / 104 page

MPC8540 Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

I2C

11.2 I2C AC Electrical Specifications

Table 40 provides the AC timing parameters for the I2C interface of the MPC8540.

Figure 17 provides the AC test load for the I2C.

Figure 29. I2C AC Test Load

Table 40. I2C AC Electrical Specifications

All values refer to VIH (min) and VIL (max) levels (see Table 39).

Parameter

Symbol 1

Min

Max

Unit

SCL clock frequency

fI2C

400

kHz

Low period of the SCL clock

tI2CL

1.3

—

μs

High period of the SCL clock

tI2CH

0.6

—

μs

Setup time for a repeated START condition

tI2SVKH

0.6

—

μs

Hold time (repeated) START condition (after this period, the

first clock pulse is generated)

tI2SXKL

0.6

—

μs

Data setup time

tI2DVKH

100

—

Data hold time:

CBUS compatible masters

I2C bus devices

tI2DXKL

—

0 2

—

0.9 3

μs

Set-up time for STOP condition

tI2PVKH

0.6

—

μs

Bus free time between a STOP and START condition

tI2KHDX

1.3

—

μs

Noise margin at the LOW level for each connected device

(including hysteresis)

VNL

0.1

× OV

—V

Noise margin at the HIGH level for each connected device

(including hysteresis)

VNH

0.2

× OV

—V

Notes:

1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH

symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C

clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I

2C timing (I2) for the time that

the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low

(L) state or hold time. Also, tI2PVKH symbolizes I

2C timing (I2) for the time that the data with respect to the stop

condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup

time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2.MPC8540 provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

3.The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.

4.CB = capacitance of one bus line in pF.

6.Guaranteed by design.

Output

OVDD/2

RL = 50 Ω

Z0 = 50 Ω

MPC8540CPX667JC 数据表(PDF) 49 Page - Freescale Semiconductor, Inc

MPC8540CPX667JC 数据表(HTML) 49 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载