MPC8540CPX667JC datasheet(16/104 Pages) FREESCALE

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MPC8540 Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

DDR SDRAM

Table 12 provides the PLL and DLL lock times.

6 DDR SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8540.

6.1 DDR SDRAM DC Electrical Characteristics

Table 13 provides the recommended operating conditions for the DDR SDRAM component(s) of the

MPC8540.

Maximum valid-to-high impedance time for actively

driven POR configs with respect to negation of HRESET

—

SYSCLKs

Notes:

1.SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8540. See the MPC8540

Integrated Processor Preliminary Reference Manual for more details.

Table 12. PLL and DLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

—

100

μs

DLL lock times

7680

122,880

CCB Clocks

1, 2

Notes:

1.DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio

results in the minimum and an 8:1 ratio results in the maximum.

2. The CCB clock is determined by the SYSCLK

× platform PLL ratio.

Table 13. DDR SDRAM DC Electrical Characteristics

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

GVDD

2.375

2.625

I/O reference voltage

MVREF

0.49

× GV

0.51

× GV

I/O termination voltage

VTT

MVREF – 0.04

MVREF + 0.04

Input high voltage

VIH

MVREF + 0.18

GVDD + 0.3

Input low voltage

VIL

–0.3

MVREF – 0.18

Output leakage current

IOZ

–10

μA5

Output high current (VOUT = 1.95 V)

IOH

–15.2

—

Output low current (VOUT = 0.35 V)

IOL

15.2

—

Table 11. RESET Initialization Timing Specifications (continued)

Parameter/Condition

Min

Max

Unit

Notes

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