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MPC8540CPX667JC 数据表(PDF) 15 Page - Freescale Semiconductor, Inc |
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MPC8540CPX667JC 数据表(HTML) 15 Page - Freescale Semiconductor, Inc |
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15 / 104 page  MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 15 RESET Initialization 4.3 RapidIO Transmit Clock Input Timing Table 9 provides the RapidIO transmit clock input (RIO_TX_CLK_IN) AC timing specifications for the MPC8540. 4.4 Real Time Clock Timing Table 10 provides the real time clock (RTC) AC timing specifications for the MPC8540. 5 RESET Initialization This section describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8540. Table 7 provides the RESET initialization AC timing specifications for the MPC8540. Table 9. RIO_TX_CLK_IN AC Timing Specifications Parameter/Condition Symbol Min Typical Max Unit Notes RIO_TX_CLK_IN frequency fRCLK 125 — — MHz RIO_TX_CLK_IN cycle time tRCLK —— 8 ns RIO_TX_CLK_IN duty cycle tRCLKH/tRCLK 48 — 52 % 1 Notes: 1. Requires ±100 ppm long term frequency stability. Timing is guaranteed by design and characterization. Table 10. RTC AC Timing Specifications Parameter/Condition Symbol Min Typical Max Unit Notes RTC clock high time tRTCH 2 x tCCB_CLK —— ns RTC clock low time tRTCL 2 x tCCB_CLK —— ns Table 11. RESET Initialization Timing Specifications Parameter/Condition Min Max Unit Notes Required assertion time of HRESET 100 — μs Minimum assertion time for SRESET 512 — SYSCLKs 1 PLL input setup time with stable SYSCLK before HRESET negation 100 — μs Input setup time for POR configs (other than PLL config) with respect to negation of HRESET 4 — SYSCLKs 1 Input hold time for POR configs (including PLL config) with respect to negation of HRESET 2 — SYSCLKs 1 |
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