MPC8540CPX667JC datasheet(56/104 Pages) FREESCALE

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MPC8540 Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

RapidIO

Figure 34 shows the DC driver signal levels.

Figure 34. DC Driver Signal Levels

13.2 RapidIO AC Electrical Specifications

This section contains the AC electrical specifications for a RapidIO 8/16 LP-LVDS device. The interface

defined is a parallel differential low-power high-speed signal interface. Note that the source of the transmit

clock on the RapidIO interface is dependent on the settings of the LGPL[0:1] signals at reset. Note that the

default setting makes the core complex bus (CCB) clock the source of the transmit clock. See Chapter 4

of the Reference Manual for more details on reset configuration settings.

13.3 RapidIO Concepts and Definitions

This section specifies signals using differential voltages. Figure 35 shows how the signals are defined. The

figure shows waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each

signal swings between A volts and B volts where A > B. Using these waveforms, the definitions are as

follows:

•

The transmitter output and receiver input signals TD, TD, RD, and RD each have a peak-to-peak

swing of A-B volts.

•

The differential output signal of the transmitter, VOD, is defined as VTD – VTD.

•

The differential input signal of the receiver, VID, is defined as VRD – VRD.

•

The differential output signal of the transmitter or input signal of the receiver, ranges from

A – B volts to – (A – B) volts.

•

The peak differential signal of the transmitter output or receiver input, is A – B volts.

VOA

VOB

RTERM

100

(no m)

VVOD = VOA – VOB

ΔV

VOHCM

VOLCM

VOSCM = (VOA + VOB)/2

–V +

ΔV

VOD = VOA – VOB

–V –

ΔV

–V

1.375 V

1.125 V

454 mV

247 mV

–247 mV

–454 mV

VOLD

Common-Mode Specifications

(c)

Differential Specifications

(b)

(a)

Note: VOA refers to voltage at output A; VOB refers to voltage at output B.

VOHD

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