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MPC8540CPX667JC 数据表(PDF) 53 Page - Freescale Semiconductor, Inc |
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MPC8540CPX667JC 数据表(HTML) 53 Page - Freescale Semiconductor, Inc |
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53 / 104 page  MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 53 PCI/PCI-X Table 44 provides the PCI-X AC timing specifications at 133 MHz. PCI-X initialization pattern to HRESET setup time tPCIVRH 10 — clocks 11 HRESET to PCI-X initialization pattern hold time tPCRHIX 050 ns 6, 11 Notes: 1.See the timing measurement conditions in the PCI-X 1.0a Specification. 2.Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test point and load circuit. 3.Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused. 4.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5.Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. 6.Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access, tPCRHFV). The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no later than two clocks before the first FRAME and must be floated no later than one clock before FRAME is asserted. 7.A PCI-X device is permitted to have the minimum values shown for tPCKHOV and tCYC only in PCI-X mode. In conventional mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock frequency. 8.Device must meet this specification independent of how many outputs switch simultaneously. 9.The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a Specification. 10.Guaranteed by characterization. 11.Guaranteed by design. Table 44. PCI-X AC Timing Specifications at 133 MHz Parameter Symbol Min Max Unit Notes SYSCLK to signal valid delay tPCKHOV — 3.8 ns 1, 2, 3, 7, 8 Output hold from SYSCLK tPCKHOX 0.7 — ns 1, 11 SYSCLK to output high impedance tPCKHOZ — 7 ns 1, 4, 8, 12 Input setup time to SYSCLK tPCIVKH 1.4 — ns 3, 5, 9, 11 Input hold time from SYSCLK tPCIXKH 0.5 — ns 11 REQ64 to HRESET setup time tPCRVRH 10 — clocks 12 HRESET to REQ64 hold time tPCRHRX 050 ns 12 HRESET high to first FRAME assertion tPCRHFV 10 — clocks 10, 12 PCI-X initialization pattern to HRESET setup time tPCIVRH 10 — clocks 12 Table 43. PCI-X AC Timing Specifications at 66 MHz (continued) Parameter Symbol Min Max Unit Notes |
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