ST7LITE49M datasheet(121/188 Pages) STMICROELECTRONICS

部件名	ST7LITE49M

功能描述	8-bit MCU with single voltage Flash memory data EEPROM, ADC, 8/12-bit timers, and I²C interface

PDF	188 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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121 / 188 page

ST7LITE49M

On-chip peripherals

121/188

Bit 1 = STOP Generation of a Stop condition bit

This bit is set and cleared by software. It is also cleared by hardware in master mode.

Note: This bit is not cleared when the interface is disabled (PE=0).

●

In master mode:

0: No stop generation

1: Stop generation after the current byte transfer or after the current Start condition is

sent. The STOP bit is cleared by hardware when the Stop condition is sent.

●

In slave mode:

0: No stop generation

1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode

the STOP bit has to be cleared by software.

Bit 0 = ITE Interrupt Enable bit

This bit is set and cleared by software and cleared by hardware when the interface is

disabled (PE=0).

0: Interrupts disabled

1: Interrupts enabled

Refer to Figure 58 for the relationship between the events and the interrupt.

SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See

Figure 57) is detected.

ST7LITE49M 数据表(PDF) 121 Page - STMicroelectronics