ST7LITE49M datasheet(118/188 Pages) STMICROELECTRONICS

118 / 188 page

On-chip peripherals

ST7LITE49M

118/188

Figure 57.

Transfer sequencing

S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge, EVx=Event (with interrupt

if ITE=1).

EV1: EVF=1, ADSL=1, cleared by reading SR1 register.

EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.

EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.

EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines

(STOP=1, STOP=0) or by writing DR register (DR=FFh). If lines are released by STOP=1, STOP=0, the

Table 41.

7-bit slave receiver:

S Address

Data1

Data2

.....

DataN

EV1

EV2

EV4

Table 42.

7-bit slave transmitter

S Address A

Data1 A

Data2 A

....

Data

EV1 EV3

EV3

EV3-

EV4

Table 43.

7-bit master receiver

Address

Data1

Data2

....

DataN

EV5

EV6

EV7

Table 44.

7-bit master transmitter

Address

Data1

Data2

....

Data

EV5

EV6 EV8

EV8

Table 45.

10-bit slave receiver

Header

Address

Data1

.....

DataN

EV1

EV2

EV4

Table 46.

10-bit slave transmitter

Sr Header A

Data1 A

...

Data

EV1 EV3

EV3

EV3-

EV4

Table 47.

10-bit master transmitter

Header A

Address A

Data1

....

DataN

EV5

EV9

EV6 EV8

EV8

Table 48.

10-bit master receiver

Header A

Data1

.....

DataN

EV5

EV6

EV7

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