ST7LITE49M datasheet(114/188 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE49M

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11.4.4

Functional description

Refer to the CR, SR1 and SR2 registers in Section 11.4.7. for the bit definitions.

By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it

initiates a transmit or receive sequence.

First the interface frequency must be configured using the FRi bits in the OAR2 register.

Slave mode

As soon as a start condition is detected, the address is received from the SDA line and sent

to the shift register; then it is compared with the address of the interface or the General Call

address (if selected by software).

Note:

In 10-bit addressing mode, the comparision includes the header sequence (11110xx0) and

the two most significant bits of the address.

●

Header matched (10-bit mode only): the interface generates an acknowledge pulse if

the ACK bit is set.

●

Address not matched: the interface ignores it and waits for another Start condition.

●

Address matched: the interface generates in sequence:

–

Acknowledge pulse if the ACK bit is set.

–

EVF and ADSL bits are set with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 register, holding the SCL line low (see

Figure 57 Transfer sequencing EV1).

Next, in 7-bit mode read the DR register to determine from the least significant bit (Data

Direction Bit) if the slave must enter Receiver or Transmitter mode.

In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It

will enter transmit mode on receiving a repeated Start condition followed by the header

sequence with matching address bits and the least significant bit set (11110xx1) .

Slave receiver

Following the address reception and after SR1 register has been read, the slave receives

bytes from the SDA line into the DR register via the internal shift register. After each byte

the interface generates in sequence:

●

Acknowledge pulse if the ACK bit is set

●

EVF and BTF bits are set with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 register followed by a read of the DR register,

holding the SCL line low (see Figure 57 Transfer sequencing EV2).

Slave transmitter

Following the address reception and after SR1 register has been read, the slave sends

bytes from the DR register to the SDA line via the internal shift register.

The slave waits for a read of the SR1 register followed by a write in the DR register, holding

the SCL line low (see Figure 57 Transfer sequencing EV3).

When the acknowledge pulse is received the EVF and BTF bits are set by hardware with an

interrupt if the ITE bit is set.

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