ST7LITE49M datasheet(116/188 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE49M

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Master mode

To switch from default Slave mode to Master mode a Start condition generation is needed.

Start condition

Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master

mode (M/SL bit set) and generates a Start condition.

Once the Start condition is sent, the EVF and SB bits are set by hardware with an interrupt if

the ITE bit is set.

The master then waits for a read of the SR1 register followed by a write in the DR register

with the Slave address, holding the SCL line low (see Figure 57 Transfer sequencing

EV5).

Slave address transmission

The slave address is then sent to the SDA line via the internal shift register.

–

In 7-bit addressing mode, one address byte is sent.

–

In 10-bit addressing mode, sending the first byte including the header sequence

causes the following event. The EVF bit is set by hardware with interrupt

generation if the ITE bit is set.

The master then waits for a read of the SR1 register followed by a write in the DR

Then the second address byte is sent by the interface.

After completion of this transfer (and acknowledge from the slave if the ACK bit is set),

the EVF bit is set by hardware with interrupt generation if the ITE bit is set.

The master waits for a read of the SR1 register followed by a write in the CR register

(for example set PE bit), holding the SCL line low (see Figure 57 Transfer sequencing

EV6).

Next the master must enter Receiver or Transmitter mode.

Note:

In 10-bit addressing mode, to switch the master to Receiver mode, software must generate

a repeated Start condition and resend the header sequence with the least significant bit set

(11110xx1).

Master receiver

Following the address transmission and after SR1 and CR registers have been accessed,

the master receives bytes from the SDA line into the DR register via the internal shift

●

Acknowledge pulse if the ACK bit is set

●

EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 register followed by a read of the DR register,

holding the SCL line low (see Figure 57 Transfer sequencing EV7).

To close the communication: before reading the last byte from the DR register, set the STOP

bit to generate the Stop condition. The interface goes automatically back to slave mode

(M/SL bit cleared).

Note:

In order to generate the non-acknowledge pulse after the last received data byte, the ACK

bit must be cleared just before reading the second last data byte.

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