AD4052BCPZ-R2 datasheet(28/66 Pages) AD

28 / 66 page

Data Sheet

AD4052/AD4058

MODES OF OPERATION

analog.com

Rev. B | 28 of 66

Table 16 shows an overview of the AD4052/AD4058 functional

modes. The ADC and serial interface functionality for each mode is

given in the subsequent sections.

Configuration mode is the default AD4052/AD4058 operating mode

following power-up and device resets. The remaining operating

modes are selected via the configuration registers as shown in Ta-

ble 16. The SPI protocol for register writes and reads is described

in the Configuration Mode section.

Figure 48 shows the AD4052/AD4058 operating mode selection

as a state machine diagram. The ENTER_ADC_MODE bit field

controls whether the AD4052/AD4058 is in configuration mode

or in one of the five ADC modes as shown in Table 16. Con-

figure the ADC_MODE and AUTO_MODE fields before setting

ENTER_ADC_MODE to 1'b1 to select the desired operating mode.

Setting the ENTER_ADC_MODE to 1'b1 via a register write triggers

the AD4052/AD4058 to transition from configuration mode to the

selected ADC mode (see Figure 46).

The exit command triggers the AD4052/AD4058 to transition from

the active ADC mode back to configuration mode. When the

AD4052/AD4058 receives the exit command, it internally resets

the ENTER_ADC_MODE bit to 1'b0. The exit command consists of

the code 5'b10101 clocked in on the SDI pin on the first 5 SCLK

rising edges following the CS falling edge. Figure 47 shows a timing

diagram for the exit command. The tCONFIG specification indicates

the minimum delay between the exit command CS rising edge and

when the AD4052/AD4058 can receive new register read and write

SPI transactions (see Table 5 and Table 6).

Table 16. AD4052/AD4058 Functional Modes

Mode

ENTER_ADC_MODE

ADC_MODE

AUTO_MODE

POWER_MODE

Configuration Mode (Default)

1'b0

Don't Care

Don't care

2'b00

Sample Mode

1'b1

2'b00

Don't care

2'b00

Burst Averaging Mode

1'b1

2'b01

Don't care

2'b00

Averaging Mode

1'b1

2'b10

Don't care

2'b00

Monitor Mode

1'b1

2'b11

1'b0

2'b00

Trigger Mode

1'b1

2'b11

1'b1

2'b00

Sleep Mode

Don't care

2'b11

Figure 46. ENTER_ADC_MODE Timing Diagram

Figure 47. Exit Command Timing Diagram

AD4052BCPZ-R2 数据表(PDF) 28 Page - Analog Devices

AD4052BCPZ-R2 数据表(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

数据表下载

链接网址

AD4052BCPZ-R2 数据表(PDF) 28 Page - Analog Devices

AD4052BCPZ-R2 数据表(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

数据表 下载

链接网址

数据表下载