AD4052BCPZ-R2 datasheet(32/66 Pages) AD

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Data Sheet

AD4052/AD4058

MODES OF OPERATION

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Rev. B | 32 of 66

BURST AVERAGING MODE

In burst averaging mode, a rising edge of the CNV signal triggers

the internal timer to perform a burst of conversions for the aver-

aging filter to accumulate and generate a 20-bit averaged result.

Table 16 lists the configuration register settings to select burst

averaging mode. Figure 53 shows a typical connection diagram for

the AD4052/AD4058 digital interface that includes a recommended

200 Ω series resistor close to the CNV pin.

Figure 54 shows an interface timing diagram for burst averaging

mode. All timing specifications in Figure 54 are given in the Timing

Specifications section. The ADC sampling period (tCYC) is set by the

internal timer frequency (fOSC) and the number of samples per burst

is set by the averaging ratio (NAVG). Table 44 lists the options for

fOSC. The averaging filter supports averaging ratios from 2 to 4096

and is set by the AVG_WIN_LEN bit field, as described in the Block

Averaging Filter section.

The digital host must wait for the averaged result to be ready before

asserting CS to start an SPI frame. The RDY signal acts as an

optional hardware interrupt to synchronize the SPI reads to the

ADC sampling phases (see the Data Ready Signal section). The

total latency between the CNV rising edge and data ready is given

by the following equation:

NAVG−1

fOSC

+tCONV

(5)

To ensure optimal performance, the digital host must also observe

the tQUIET specification that defines the minimum delay between the

final SCLK falling edge and the next CNV rising edge.

By default, the burst averaging mode output are 24-bits long, in-

cluding the 20-bit averaged ADC data with 4-bits of sign extension.

Burst averaging mode also offers an optional sign extension byte

and CRC byte that can be appended to the 24-bit data. See the

ADC Mode Output Data Format section for details on the burst

averaging mode SDO data formatting options.

When the DEV_EN signal is enabled, the start of the burst of con-

versions is delayed by the programmable tPWR_ON delay, relative to

the CNV rising edge. The DEV_EN signal remains asserted until

the end of the burst of samples. See the Device Enable Signal

section and Figure 57 for specific timing details when using the

DEV_EN signal.

Figure 53. Burst Averaging Mode Example Connection Diagram

Figure 54. Burst Averaging Mode Timing Diagram

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