AD4052BCPZ-R2 datasheet(48/66 Pages) AD

48 / 66 page

Data Sheet

AD4052/AD4058

APPLICATIONS INFORMATION

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Rev. B | 48 of 66

uring and calculating the MON_VAL digital correction factor. Figure

77 shows the configuration after MON_VAL is updated and the

AD4052/AD4058 begin sampling the inputs with VDD as the VREF

source. Table 20 gives the relevant configuration settings for both

phases.

In the MON_VAL calculation phase, the REF pin is driven by an

accurate voltage reference, like the MAX6070, and the REF pin is

selected as the VREF source. The VDD voltage is internally scaled

by ½ and sampled by the ADC. A CNV rising edge triggers a burst

of samples in burst averaging mode. When the averaged result

is generated, the AD4052/AD4058 automatically calculate a 16-bit

digital correction factor and load it into the MON_VAL field. The

RDY signal can optionally be assigned to the GP0 or GP1 pins to

indicate when the calculation is complete.

In the MON_VAL application phase, the ADC is reconfigured to

sample the input signal via the IN+ and IN− pins, with VDD selected

as the VREF source. The external voltage reference is powered

down to reduce system power. When the ADC samples the inputs,

the MON_VAL scaling factor is applied to the digital output codes to

scale them to the transfer function set by the REF voltage instead

of the VDD voltage.

Depending on the stability of the VDD supply circuit, the MON_VAL

calculation may need to be repeated periodically to maintain system

accuracy targets.

Figure 76. MON_VAL Calculation Configuration

Figure 77. MON_VAL Application Configuration

AD4052BCPZ-R2 数据表(PDF) 48 Page - Analog Devices