AD4052BCPZ-R2 datasheet(35/66 Pages) AD

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Data Sheet

AD4052/AD4058

MODES OF OPERATION

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Rev. B | 35 of 66

4. VIN ≤ MIN_LIMIT

The comparator includes two hardware alert signals for the maxi-

mum and minimum threshold events (MAX_INTR and MIN_INTR,

respectively). These signals can be assigned to either or both

of the GP0 and GP1 pins, as described in the Threshold Alert

Signals section. Figure 63 shows a typical connection diagram for a

microcontroller using these alert signals as hardware interrupts.

Monitor Mode

In monitor mode, the AD4052/AD4058 continuously operate in

autonomous mode until the digital host sends the exit command

to put it back into configuration mode (see Figure 48). Monitor

mode makes use of the user-programmable hysteresis settings to

self-clear the MAX_INTR and MIN_INTR signals when the input

signal goes back in range (see Figure 43).

Figure 61 shows a flowchart for register configuration, the com-

parison sequence operations, and the behavior of the hardware

interrupts and alert flags following threshold crossings in monitor

mode. Table 16 lists the configuration register settings to select

monitor mode.

When the maximum or minimum threshold crossings are detected,

the MAX_INTR or MIN_INTR signal asserts, respectively. The

internal timer continues to generate the sampling clock, and the

MAX_INTR or MIN_INTR signal is deasserted when the sampled

input signal is back in bounds as set by the MAX_HYST and

MIN_HYST bit fields, respectively.

The MAX_FLAG or MIN_FLAG bit is also asserted when

MAX_INTR or MIN_INTR asserts, respectively. The MAX_FLAG

and MIN_FLAG are sticky and do not self-clear when the signal

goes back in range. It is recommended to reset the MAX_FLAG

and MIN_FLAG bits after sending the exit command and before

returning to autonomous mode.

Figure 61. Monitor Mode Flowchart

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