AD4052BCPZ-R2 datasheet(50/66 Pages) AD

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Data Sheet

AD4052/AD4058

APPLICATIONS INFORMATION

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Rev. B | 50 of 66

CALCULATING SERIAL INTERFACE OUTPUT

DATA RATE

The AD4052/AD4058 ADC core performance is specified for fS up

to 2 MSPS/500 kSPS, but the maximum achievable output data

rate (fODR_MAX) is a function of the serial interface specifications

and may limit the practical fS. In sample mode and averaging

mode, for example, the digital host must read the entire ADC result

between the end of the previous conversion and the start of the

next conversion, or else the result is lost. Therefore, the maximum

fS and the minimum sample period (tCYC) for a given application

using these modes is a function of the AD4052/AD4058 and digital

host timing specifications.

In burst averaging mode and the autonomous modes, the ADC

sampling rate is set by the internal timer (see the Internal Timer

section). The serial interface does not limit the sampling rate in

these modes because the digital host does not have to read out an

entire sample within one conversion period.

Figure 80 illustrates the timing restrictions for reading out ADC

data in sample mode and averaging mode. The minimum tCYC

for sample mode and averaging mode can be estimated with the

following equations:

tCYC_MIN=tCONV+tEN+tQUIET+tSCLK×

NBITS−12

(10)

fODR_MAX= 1tCYC_MIN

(11)

where:

tCYC_MIN is the minimum achievable sample period.

fODR_MAX is the maximum achievable output data rate.

tCONV is the maximum conversion time specification.

tEN is the maximum delay between CS falling edge and valid data

on SDO.

tQUIET is the minimum quiet time specification.

tSCLK is the serial clock period.

NBITS is the length of the ADC data packet in bits.

The default values for NBITS are 16 bits for sample mode and 20

bits for averaging mode (see the ADC Mode Output Data Format

section for all options of NBITS for each operating mode).

The AD4052/AD4058 uses SPI Mode 0 (CPOL = CPHA = 0), so the

MSB is launched on the SDO pin following each CS falling edge,

with a delay given by the tEN specification. Equation 10 assumes

the first SCLK rising edge occurs as quickly as possible while

adhering to the tEN specification, but the CS falling edge to SCLK

rising edge delay may vary between digital hosts.

The fastest (minimum) tSCLK periods in Table 5 and Table 6 are

only achievable for digital hosts that can latch SDO data on the

falling edge of SCLK, such as FPGAs, because the maximum tDSDO

delay is longer than half of the minimum tSCLK specification. For

standard microcontrollers interfacing with the AD4052/AD4058, da-

ta are latched on the SCLK rising edges, so the minimum practical

tSCLK is at least 2 × tDSDO. Table 21 provides examples of fODR_MAX

using Equation 10 and Equation 11 and assuming tSCLK = 2 ×

tDSDO instead of the minimum tSCLK specifications in the Timing

Specifications.

Note that the tDSDO delay is specified for a CLOAD of 20 pF. The

estimates in Table 21 do not account for differences in CLOAD,

the setup and hold time specifications of the digital host SPI, or

additional sources of delay within the digital host SPI transactions

(for example, delays to transfer SPI data buffer contents to other

peripherals or the latency of its interrupt handler). The practical

serial clock rate varies between applications and must be independ-

ently verified.

Figure 80. Sample Mode and Averaging Mode Serial Interface Readback Timing

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