AD4052BCPZ-R2 datasheet(57/66 Pages) AD

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Data Sheet

AD4052/AD4058

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Rev. B | 57 of 66

Table 36. Bit Descriptions for INTERFACE_STATUS

Bits

Bit Name

Description

Reset

Access

NOT_RDY_ERROR

Interface Not Ready Error. This error bit is set if the user attempts to execute an SPI transaction before the

completion of digital initialization. For example, before a device reset is complete.

0x0

R/W1C

[6:5]

RESERVED

Reserved.

0x0

SCLK_ERROR

SPI Clock Count Error. This error bit is set when an incorrect number of serial clock periods is received in a

configuration mode SPI transaction. For example, if the data phase does not contain an integer multiple of

8 SCLK periods.

0x0

R/W

CRC_ERROR

Interface CRC Error. This error bit is set when the device receives an invalid CRC checksum value on SDI

(in configuration mode). This error bit is only active when CRC is enabled.

0x0

R/W1C

WRITE_INVALID

Invalid Write Error Flag. This error bit is set to 1 when the digital host attempts a register write to a register

that contains exclusively read-only bits.

0x0

R/W1C

PARTIAL_ERROR

Partial Register Access Error. This error bit is set to 1 when the digital host fails to read or write

from both bytes of a 2-byte register (in configuration mode). For example, terminating a read from the

MAX_LIMIT_REG register after reading only 1 of its 2 bytes.

0x0

R/W1C

ADDR_INVALID

Invalid Register Address Error. This error bit is set to 1 when the digital host attempts to read from or write

to an undefined register address.

0x0

R/W1C

DEVICE MODE SELECT REGISTER

Address: 0x20, Reset: 0x00, Name: MODE_SET

Table 37. Bit Descriptions for MODE_SET

Bits

Bit Name

Description

Reset

Access

[7:1]

RESERVED

Reserved.

0x0

ENTER_ADC_MODE

Exit Configuration Mode. Write 1 to exit configuration mode at the next CSB rising edge. The device

enters the operating mode selected by the ADC_MODE and AUTO_MODE bits. This bit is cleared

automatically by the exit command.

0x0

R0/W

ADC OPERATING MODE CONFIGURATION REGISTER

Address: 0x21, Reset: 0x80, Name: ADC_MODES

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