AD4052BCPZ-R2 datasheet(42/66 Pages) AD

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Data Sheet

AD4052/AD4058

SERIAL INTERFACE

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Rev. B | 42 of 66

DEVICE RESET

A device reset returns the device registers to the default settings

and puts the AD4052/AD4058 into configuration mode. The fol-

lowing sections describe the AD4052/AD4058 device reset mecha-

nisms.

The AD4052/AD4058 include a hardware interrupt signal

(DEV_RDY) that indicates when the device reset is complete. The

DEV_RDY signal is active high and is assigned to the GP1 pin by

default, so the digital host can monitor the GP1 pin for a rising edge

to inform the firmware that the AD4052/AD4058 SPI is ready. See

the Device Ready Signal for more information.

The DEVICE_RESET bit in the DEVICE_STATUS register indicates

when a device reset has occurred. The DEVICE_RESET bit is a

write-1-to-clear bit and holds its state until the host writes it to the

value 1'b1. The DEVICE_RESET bit can be referenced to confirm a

reset executed as expected or if an unintended reset occurred (for

example, if the power supplies failed during operation).

Reset Bits

A reset is initiated by setting both the SW_RESET and SW_RE-

SETX bits in the INTERFACE_CONFIG_A register to 1'b1 in the

same write instruction (see the Interface Configuration A Register

section). Two reset bit fields are used to reduce the likelihood of

an unintended reset from interference on the SPI signals. The reset

bits are only available in configuration mode, because they are

located in the INTERFACE_CONFIG_A configuration register.

Figure 69 shows the timing diagram for resetting the AD4052/

AD4058 with the reset bits. The digital host must wait for the tRESET

delay to elapse before initiating SPI transactions (see Table 1).

Reset Pattern

The reset pattern shown in Figure 70 allows the digital host to

reset the AD4052/AD4058 from any of its operating modes. The

reset pattern is equivalent to an 18-byte SPI write with the code

48'hFFFF FFFF FFFE repeated three times.

Figure 70 shows the timing diagram for resetting the AD4052/

AD4058 with the reset bits. The digital host must wait for the tRESET

delay to elapse before initiating SPI transactions (see Table 1).

Power-On Reset

The AD4052/AD4058 is designed to generate a power-on reset

(POR) when the VDD and VIO rails are first applied or when the

rails are power cycled. A POR on the VDD or VIO supplies resets

the state of the user configuration registers. The configuration regis-

ters are not reset when the AD4052/AD4058 enter sleep mode and

disable the internal LDO regulator (see the Sleep Mode section).

Figure 71 shows the timing diagram for the AD4052/AD4058 PORs.

The digital host must wait for the tRESET delay after the power

supplies are stable. Then the digital host must perform a reset with

the reset bits or the reset pattern. Finally, an additional tRESET delay

must elapse before performing other SPI transactions.

Figure 69. Reset Bit Timing Diagram

Figure 70. Reset Pattern Timing Diagram

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