AD4052BCPZ-R2 datasheet(21/66 Pages) AD

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Data Sheet

AD4052/AD4058

THEORY OF OPERATION

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Rev. B | 21 of 66

DIGITAL PROCESSING FEATURES

Figure 40. AD4052/AD4058 Digital Processing Functionality

The AD4052/AD4058 include several data processing features that

can be applied to ADC data to offload computations from the digital

host processor. Figure 40 shows a block diagram of the available

data processing functions. Functionality and configuration of each

block is described in detail in following sections. Note that these

digital processing functions are not used in the autonomous modes.

Gain Scaling

The gain scaling function applies a 16-bit unsigned digital gain

factor to the 16-bit ADC results. Gain scaling can be applied to

calibrate out system gain error. The gain scaling factor is set by

the MON_VAL bit field in the MON_VAL scaling register with the

following equation:

CodeOUT=CodeIN× MON_VAL0x8000

(1)

where 0x0000 ≤ MON_VAL ≤ 0xFFFF, giving an effective gain

range of 0 to 1.99997.

Gain scaling can also be used to scale the ADC transfer function

when using the VDD supply as the VREF source (see the Reference

Selection Modes section). The AD4052/AD4058 can be configured

to measure the ratio of the VDD supply and the REF input voltage

and automatically adjust the MON_VAL register value to set the

transfer functions to be the same. The external voltage reference

circuitry can then be powered down to reduce system power dissi-

pation. See the Achieving High Accuracy with Reference Shutdown

section for more information.

Note that applying gain to the samples can cause numerical satu-

ration when CodeOUT in Equation 1 exceeds the 16-bit full scale

(see the Full-Scale Saturation section). Ensure the MON_VAL bit

field is set accordingly to prevent the gain scaling block output from

saturating.

Gain scaling is disabled by default and enabled by setting the

SCALE_EN bit field in the ADC_CONFIG register to 1 (see Table

39).

Full-Scale Saturation

The conversion results saturate digitally (prior to any data process-

ing) when the sampled analog input voltage exceeds the input

range limits specified in Table 1. The AD4052/AD4058 include

saturation blocks at the output of the ADC core and the output of

the gain scaling block that detect when the digital output codes

or the ADC core and gain scaling block reach the maximum or

minimum values, respectively.

The OVER_RNG_ERR and UNDER_RNG_ERR flags in the DE-

VICE_STATUS register are set when either of the saturation blocks

detect a maximally or minimally saturated code. In differential

mode, the 16-bit results saturate maximally at 0x7FFF and mini-

mally at 0x8000. In single-ended mode the 16-bit results saturate

maximally at 0xFFFF and minimally at 0x0000. (See the Transfer

Function section for a description of differential and single-ended

modes.)

The OVER_RNG_ERR and UNDER_RNG_ERR flags can be peri-

odically polled when using the block averaging filter to verify none

of the filter input data has saturated. The OVER_RNG_ERR and

UNDER_RANGE_ERR flags are write-1-to-clear bits, and therefore,

hold their states until the digital host is able to poll them.

Block Averaging Filter

The AD4052/AD4058 include a block averaging filter with program-

mable averaging ratios (NAVG) from 2 to 4096. The block averaging

filter is automatically enabled when the device is in averaging

mode or burst averaging mode. The block averaging filter exhibits

a SINC1 frequency response. Figure 41 shows the frequency

response of the averaging filter for NAVG of 2, 4, 8, 16, and 32.

When enabled, the block averaging filter accumulates a block of

16-bit ADC results before generating a 20-bit averaged result.

NAVG refers to the number of ADC samples per averaged result.

The block averaging filter is reset (cleared) after processing each

block of NAVG samples. The NAVG configuration is set by the

AVG_WIN_LEN bit field in the AVG_CONFIG register (see Table

40) using the following equation:

NAVG=2AVG_WIN_LEN+1

(2)

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