AD4052BCPZ-R2 datasheet(49/66 Pages) AD

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Data Sheet

AD4052/AD4058

APPLICATIONS INFORMATION

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Rev. B | 49 of 66

Table 20. Configuration Settings for MON_VAL Scaling

Bit Field Name

MON_VAL Calculation

MON_VAL Application

REF_SEL

1'b0: VREF = REF

1'b1: VREF = VDD

DATA_FORMAT

1'b0: Single-ended mode Don't care

INP_MUX_SEL

2'b10: Sample VDD/2

2'b00: Sample IN+ and

IN−

ADC_MODE

2'b10: Burst averaging

mode

Don't care

AVG_WIN_LEN

Don't care1

Don't care

SCALE_EN

1'b0: Scaling disabled

1'b1: Scaling enabled

GP0_SEL

3'b010: RDY on GP02

Don't care

GP1_SEL

3'b110: Logic high on

GP13

3'b011: Logic low on GP13

1 MON_VAL calculations do not require a specific value for NAVG, but it is

recommended to set NAVG based on the VDD supply circuit noise and the

system accuracy targets.

2 Optional. The RDY signal can act as a hardware interrupt to notify the digital

host when MON_VAL calculation is complete.

3 Optional. The static logic levels can act as the voltage reference enable pin

if its input logic levels are consistent with the AD4052/AD4058 output logic

levels.

VDD POWER DISSIPATION

SAR ADCs such as the AD4052/AD4058 are ideal for precision

measurement applications with tight power dissipation budgets. The

ADC core is effectively duty-cycled and only consumes active pow-

er while performing a conversion, so the effective power dissipation

is lower at slower sample rates. Figure 78 illustrates the instantane-

ous and average VDD input current (IDD) vs. ADC sampling. Table 1

gives the average supply current and power dissipation for several

operating modes and sample rates.

The AD4052/AD4058 ADC core is exceptionally power efficient and

can operate in several lower power operating modes. As described

in the Analog Front-End Design section, slower sampling rates

also relax the load drive requirements for the AFE and reference

circuitry, allowing the AD4052/AD4058 to interface with low-power

amplifiers and voltage references for overall system power optimi-

zation.

While the AD4052/AD4058 is idle, VDD draws only 990 nA standby

current (see Figure 32). In sample mode and averaging mode,

the AD4052/AD4058 average VDD current is 0.4 mA at 1 MSPS,

and 0.2 mA at 500 kSPS, equivalent to 400 pC per conversion.

In the autonomous modes, the VDD current is reduced to 112 μA

at 1 MSPS, and 56 μA at 500 kSPS, equivalent to 112 pC per

comparison operation. Figure 24 and Figure 27 show the average

IDD and power dissipation vs. the ADC sample rate and operating

mode. The supply current and power dissipation scale linearly with

the sample rate.

In burst averaging mode, the AD4052/AD4058 performs a burst of

conversions to generate an averaged result. The average power

dissipation in burst averaging mode is, therefore, a function of the

average number of conversions performed per second over many

bursts of samples. This is a function of the burst sampling rate,

NAVG, and the period of the CNV signal. Figure 79 illustrates the

VDD power dissipation over the burst sampling and idle phases in

burst averaging mode.

Figure 78. IDD vs. Conversion Periods in Sample Mode and Averaging Mode

Figure 79. IDD vs. Burst Conversions in Burst Averaging Mode

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