Data Sheet

AD4052/AD4058

SPECIFICATIONS

analog.com

Rev. B | 8 of 66

Table 4. SPI Timing—Configuration Mode, VIO ≥ 1.71 V

Parameter1

Symbol

Min

Typ

Max

Unit

CS High Time

tCSH

15

ns

CS Falling Edge to SDO Valid

tEN

20

ns

CS Rising Edge to SDO High Impedance

tCSDIS

20

ns

SCLK Period

tSCLK

62.5

ns

SCLK Low Time

tSCLKL

25

ns

SCLK High Time

tSCLKH

25

ns

SDI Valid Setup Time Prior to SCLK Rising Edge (SDI Setup Time)

tSSDI

10

ns

SDI Valid Hold Time After SCLK Rising Edge (SDI Hold Time)

tHSDI

4

ns

SCLK Falling Edge to Data Remains Valid (SDO Hold Time)

tHSDO

2

ns

SCLK Falling Edge to Data Valid (SDO Valid Delay)

tDSDO

22

ns

Operating Mode Update Delay

tMODE

62.5

ns

Reset Delay

tRESET

5

ms

1 The tSCLK, tSCLKL, and tSCLKH specifications are production tested. All other timing specifications in this table are guaranteed by characterization and design.

Table 5. SPI Timing—ADC Modes, VIO ≥ 3.0 V

Parameter1

Symbol

Min

Typ

Max

Unit

CS Falling Edge to SDO Valid

tEN

8

ns

CS Rising Edge to SDO High Impedance

tCSDIS

8

ns

SCLK Period

tSCLK

12

ns

SCLK Low Time

tSCLKL

5.4

ns

SCLK High Time

tSCLKH

5.4

ns

SDI Valid Setup Time Prior to SCLK Rising Edge (SDI Setup Time)

tSSDI

4

ns

SDI Valid Hold Time After SCLK Rising Edge (SDI Hold Time)

tHSDI

2

ns

SCLK Falling Edge to Data Remains Valid (SDO Hold Time)

tHSDO

1.5

ns

SCLK Falling Edge to Data Valid (SDO Valid Delay)

tDSDO

8

ns

Exit Command to Register Access Delay

tCONFIG

8

ns

Reset Delay

tRESET

5

ms

1 The tSCLK, tSCLKL, and tSCLKH specifications are production tested. All other timing specifications in this table are guaranteed by characterization and design.

Table 6. SPI Timing—ADC Modes, VIO ≥ 1.71 V

Parameter1

Symbol

Min

Typ

Max

Unit

CS Falling Edge to SDO Valid

tEN

15

ns

CS Rising Edge to SDO High Impedance

tCSDIS

15

ns

SCLK Period

tSCLK

17

ns

SCLK Low Time

tSCLKL

7.5

ns

SCLK High Time

tSCLKH

7.5

ns

SDI Valid Setup Time Prior to SCLK Rising Edge (SDI Setup Time)

tSSDI

5

ns

SDI Valid Hold Time After SCLK Rising Edge (SDI Hold Time)

tHSDI

4

ns

SCLK Falling Edge to Data Remains Valid (SDO Hold Time)

tHSDO

1.5

ns

SCLK Falling Edge to Data Valid (SDO Valid Delay)

tDSDO

15

ns

Exit Command to Register Access Delay

tCONFIG

15

ns

Reset Delay

tRESET

5

ms

1 The tSCLK specification is production tested. All other timing specifications in this table are guaranteed by characterization and design.