AD4052BCPZ-R2 datasheet(45/66 Pages) AD

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Data Sheet

AD4052/AD4058

APPLICATIONS INFORMATION

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Rev. B | 45 of 66

ANALOG FRONT-END DESIGN

Wide Input Common-Mode Range

The AD4052/AD4058 analog inputs feature a wide common-mode

input voltage range that is only restricted by the absolute voltage

range for each input (see Table 1). The IN+ and IN− signals

can span anywhere between 0 V and VREF without violating the

common-mode input voltage specification (VCM), ensuring compati-

bility with both differential and single-ended type signals. The VCM

voltage is given in the following equation and illustrated in Figure

73.

The AD4052/AD4058 convert the differential voltage between IN+

and IN−, and the common-mode signal is attenuated by the CMRR

(see Table 1 and Figure 18).

VCM=VIN++VIN−2

(7)

Figure 73. AD4052/AD4058 Wide Input Common-Mode Range

AD4052/AD4058 Equivalent Analog Input Model

As described in the Analog Inputs section, the AD4052/AD4058

analog inputs can be modeled as switched capacitive loads, with

the IN+ and IN− inputs each connected to a 3.4 pF sampling capac-

itor through a set of sampling switches (SW1). As part of each

conversion phase, the SW1 switch disconnects and reconnects

the sampling capacitors (CIN) from the IN+ and IN− pins, causing

transient input current and voltage glitches at the output of the

AFE circuit. The small CIN of the AD4052/AD4058 ensures the

magnitude of the transient current and voltage spikes is minimal

compared to other SAR ADCs, but the AFE must still be designed

to settle these glitches quickly enough (before the next conversion)

to meet the accuracy and performance specifications in Table 1.

Figure 74 shows an equivalent load circuit model of the AD4052/

AD4058 IN+ and IN− inputs. SW1 represents the sampling switches

and SW2 represents the CIN reset switch. The SW1 switch opens at

the beginning of the conversion phase to sample the IN+ and IN−

voltages on the CIN capacitors. Before the start of the acquisition

phase, the SW2 switch shorts the sampling capacitors together

to reset them to a known, predictable state. Because the CIN

capacitance is the same for both IN+ and IN−, the reset voltages

on each capacitor are equivalent and are given by the following

equation:

VIN++VIN−

(8)

where VIN+ and VIN− are the sampled IN+ and IN− voltages, respec-

tively. Note that this formula is the same as the common-mode input

voltage formula given in Equation 7.

As mentioned in the Converter Operation section, the AD4052/

AD4058 acquisition and conversion phases overlap. The acquisition

phase starts 210 ns after the start of the conversion phase. At

the start of the acquisition phase, the SW2 switch opens and the

SW1 switch closes to reconnect CIN to the AD4052/AD4058 inputs

to acquire the signal. At the instant SW1 closes, the IN+ and IN−

inputs sink or source some charge from the AFE circuit to recharge

the CIN capacitors to the intended signal voltage. The transient

current spike causes transient voltage glitches on each pin, with

magnitudes that are a function of the amount of charge pulled by

the CIN capacitors and the output impedance of the AFE circuit.

The SW2 switch is implemented to minimize linearity errors if

the AFE cannot completely settle the input glitch before the next

conversion phase. The SW2 switch ensures the charge transfer per

sample is linearly related to the input signal voltage. The worst-case

current and voltage glitch magnitude occur when the differential

input voltage is equal to VREF. For example, when VIN− = 0 V, and

VIN+ = VREF = 3.3 V, the charge transfer per sample is 5.6 pC

into the IN− input and out of the IN+ input. The steady-state input

current is, therefore, also linearly related to input voltage, as shown

in Figure 20. Settling error with the AD4052/AD4058, therefore,

appears as additional gain error rather than degradation in INL and

THD.

An RC kickback filter is recommended on each of the IN+ and IN−

pins to attenuate the voltage glitch on the output of the AFE circuit

(see Figure 72). The Front-End Amplifier and RC Filter Design

for a Precision SAR Analog-to-Digital Converter article provides

guidance for selecting the RC components of the kickback filter to

ensure proper settling. Table 19 provides general RC component

recommendations for the AD4052/AD4058 for several sample rates

(RFILT and CFILT are the resistor and capacitor values in the RC

kickback filter, respectively). The values in Table 19 are provided for

initial guidance, and the system designer must verify the companion

amplifier is stable driving these RC loads.

The AD4052/AD4058 LTspice model emulates the equivalent ana-

log input model shown in Figure 74 when configured for transient

simulations.

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