AD4052BCPZ-R2 datasheet(22/66 Pages) AD

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Data Sheet

AD4052/AD4058

THEORY OF OPERATION

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Rev. B | 22 of 66

Figure 41. Frequency Response Examples for the Block Averaging Filter

INTERNAL TIMER

The AD4052/AD4058 include an internal timer to generate the

ADC sampling clock in burst averaging mode and autonomous

modes. The sampling frequency in these modes is set by the

FS_BURST_AUTO bit field in the TIMER_CONFIG register and

ranges from 2 MSPS to 111 SPS. See Table 44 in the Register

Details section for the full set of nominal sampling clock frequen-

cies (fOSC) offered on the AD4052/AD4058. The actual sampling

frequency in these modes is guaranteed to be within ±15% of fOSC

(see Table 2). Note that the 2 MSPS and 1 MSPS settings are

invalid for the AD4058. On the AD4058, the FS_BURST_AUTO

averaging mode or the autonomous modes.

The internal timer also controls the DEV_EN signal delay (see the

Device Enable Signal section). The tPWR_ON delay is set by the

TIMER_PWR_ON bit field, which is also in the TIMER_CONFIG

Table 44 in the Register Details section for the full set of nominal

tPWR_ON delay options.

POWER SUPPLIES

The AD4052/AD4058 have the following three power domains, the

ranges for which are given in Table 1:

►

VDD is the analog supply rail.

►

CLDO is the +1.8 V ADC core supply rail, generated by an

internal +1.8 V LDO regulator.

►

VIO is the digital interface logic supply rail.

The VDD and VIO supplies must be supplied externally. The CLDO

supply is generated internally by an internal +1.8 V LDO regulator

sourced by the VDD rail. The VDD supply current is a function of

the ADC sampling rate, because it supplies the internal LDO regu-

lator that then supplies the SAR ADC core (see the VDD Power

Dissipation section). In sleep mode, the internal LDO regulator is

powered down to reduce the VDD standby current to 10 nA (see

Table 1 and the Sleep Mode section).

The AD4052/AD4058 have no power supply sequencing require-

ments. The minimum allowable rise time for the VDD and VIO

supplies is 100 μs. It is recommended to perform a device reset

after the VDD and VIO supplies are stable (see the Power-On

Reset section).

It is recommended to decouple the VDD, CLDO, and VIO pins to

GND each with a 1 μF capacitor. When selecting VDD as the VREF

source (as described in the Reference Selection Modes section),

or when driving the VDD and REF pins with a common external

source, it is recommended to decouple VDD and REF with a shared

2.2 μF capacitor.

COMPARATOR OPERATION

The AD4052/AD4058 ADC cores offer a lower power, 16-bit win-

dow comparator mode for autonomous threshold detection and

monitoring. Figure 42 shows a simplified schematic of the window

comparator used in the autonomous modes.

The AD4052/AD4058 have two autonomous sampling modes, as

described in the Autonomous Modes section. When either of

the autonomous modes are enabled, the ADC enters comparator

mode, and the internal timer acts as the sampling clock (see the

Internal Timer section). The comparator steps through a sequence

of comparisons against four user-programmable threshold regions

on each sample and generates alert flags and hardware interrupts

when the signal enters those regions.

Figure 43 illustrates the out-of-bounds regions set by the max-

imum and minimum threshold values. The maximum and mini-

mum thresholds are user-programmable via the MAX_LIMIT and

MIN_LIMIT bit fields. The MAX_LIMIT and MIN_LIMIT fields are

each 12 bits wide for 12-bit comparator resolution. There are also

independent hysteresis settings for maximum and minimum limits,

set by the MAX_HYST and MIN_HYST fields, respectively, that

define a second set of limits for autoclearing the alert signals. See

the Autonomous Modes section for more information.

The data format of the MAX_LIMIT and MIN_LIMIT fields corre-

sponds to the selected input range mode (as described in the

Transfer Function section). The MAX_LIMIT and MIN_LIMIT fields

are in twos complement in differential mode (DATA_FORMAT =

1'b1) and straight binary in single-ended mode (DATA_FORMAT =

1'b0). The MAX_HYST and MIN_HYST fields are always straight

binary regardless of input mode setting.

The comparator includes two alert signals and two sticky alert

bits in the register map. The MAX_INTR and MIN_INTR signals

are the alert signals for maximum and minimum threshold events,

respectively. The MAX_INTR and MIN_INTR signals may be routed

to either or both of the GP0 and GP1 pins (see the Interrupts and

Control Signals section). The MAX_FLAG and MIN_FLAG bits are

sticky, write 1 to clear the bits in the DEVICE_STATUS register.

The DEVICE_STATUS register also includes a threshold overrun bit

(THRESH_OVERRUN) that is set whenever the comparator tries to

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