DP83867CS datasheet(26/129 Pages) TI2

26 / 129 page

7.4.1.2 Reduced GMII (RGMII)

The Reduced Gigabit Media Independent Interface (RGMII) is designed to reduce the number of pins required to

interconnect the MAC and PHY (12 pins for RGMII relative to 24 pins for GMII). To accomplish this goal, the data

paths and all associated control signals are reduced and are multiplexed. Both rising and trailing edges of the

clock are used. For Gigabit operation the GTX_CLK and RX_CLK clocks are 125MHz, and for 10- and 100Mbps

operation, the clock frequencies are 2.5MHz and 25MHz, respectively.

For more information about RGMII timing, see the RGMII Interface Timing Budgets application report

(SNLA243).

7.4.1.2.1 1000Mbps Mode Operation

All RGMII signals are positive logic. The 8-bit data is multiplexed by taking advantage of both clock edges. The

lower 4 bits are latched on the positive clock edge and the upper 4 bits are latched on trailing clock edge. The

control signals are multiplexed into a single clock cycle using the same technique.

To reduce power consumption of RGMII interface, TXEN_ER and RXDV_ER are encoded in a manner that

minimizes transitions during normal network operation. This is done by following encoding method. Note that the

value of GMII_TX_ER and GMII_TX_EN are valid at the rising edge of the clock. In RGMII mode, GMII_TX_ER

is presented on TX_CTRL at the falling edge of the GTX_CLK clock. RX_CTRL coding is implemented the same

fashion.

When receiving a valid frame with no error, RX_CTRL = True is generated as a logic high on the rising edge of

RX_CLK and RX_CTRL = False is generated as a logic high at the falling edge of RX_CLK. When no frame is

being received, RX_CTRL = False is generated as a logic low on the rising edge of RX_CLK and RX_CTRL =

False is generated as a logic low on the falling edge of RX_CLK.

TX_CTRL is treated in a similar manner. During normal frame transmission, the signal stays at a logic high for

both edges of GTX_CLK and during the period between frames where no error is indicated, the signal stays low

for both edges.

7.4.1.2.2 1000Mbps Mode Timing

The DP83867 provides configurable clock skew for the GTX_CLK and RX_CLK to optimize timing across the

interface. The transmit and receive paths can be optimized independently. Both the transmit and receive path

support 16 programmable RGMII delay modes through register configuration. Strap configuration can also be

used to configure 8 programmable RGMII modes for both the transmit and receive paths. See Section 7.5.1 for

details.

The timing paths can either be configured for Aligned mode or Shift mode. In Aligned mode, no clock skew is

introduced. In Shift mode, the clock skew can be introduced in 0.5ns increments (through strap configuration)

or in 0.25ns increments (through register configuration). Configuration of the Aligned mode or Shift mode is

accomplished through the RGMII Control Register (RGMIICTL), address 0x0032. In Shift mode, the clock skew

can be adjusted using the RGMII Delay Control Register (RGMIIDCTL), address 0x0086.

7.4.1.2.3 10- and 100Mbps Mode

When the RGMII interface is operating in the 100Mbps mode, the Ethernet Media Independent Interface (MII)

is implemented by reducing the clock rate to 25MHz. For 10Mbps operation, the clock is further reduced to

2.5MHz. In the RGMII 10/100 mode, the transmit clock RGMII TX_CLK is generated by the MAC and the receive

clock RGMII RX_CLK is generated by the PHY. During the packet receiving operation, the RGMII RX_CLK can

be stretched on either the positive or negative pulse to accommodate the transition from the free-running clock

to a data synchronous clock domain. When the speed of the PHY changes, a similar stretching of the positive or

negative pulses is allowed. No glitch is allowed on the clock signals during clock speed transitions.

This interface operates at 10- and 100Mbps speeds the same way as at 1000Mbps mode with the exception that

the data can be duplicated on the falling edge of the appropriate clock.

The MAC holds the RGMII TX_CLK low until the MAC has confirmed that the MAC is operating at the same

speed as the PHY.

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

www.ti.com

Submit Document Feedback

Product Folder Links: DP83867CS DP83867IS DP83867E

DP83867CS 数据表(PDF) 26 Page - Texas Instruments

DP83867CS 数据表(HTML) 26 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载