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DP83867CS 数据表(PDF) 4 Page - Texas Instruments |
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DP83867CS 数据表(HTML) 4 Page - Texas Instruments |
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4 / 129 page  5.1 Pin Functions Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. MAC INTERFACES (SGMII, RGMII) TX_D3 25 I, PD TRANSMIT DATA Bit 3: This signal carries data from the MAC to the PHY in RGMII mode. This pin is synchronous to the transmit clock GTX_CLK. TX_D2 26 I, PD TRANSMIT DATA Bit 2: This signal carries data from the MAC to the PHY in RGMII mode. This pin is synchronous to the transmit clock GTX_CLK. SGMII_SIP 27 I, PD Differential SGMII Data Input: This signal carries data from the MAC to the PHY in SGMII mode. This pin is synchronous to the differential SGMII clock input. This pin can be AC-coupled to the MAC through a 0.1µF capacitor when operating in SGMII mode. TX_D1 27 I, PD TRANSMIT DATA Bit 1: This signal carries data from the MAC to the PHY in RGMII mode. This pin is synchronous to the transmit clock GTX_CLK. SGMII_SIN 28 I, PD Differential SGMII Data Input: This signal carries data from the MAC to the PHY in SGMII mode. This pin is synchronous to the differential SGMII clock input. This pin can be AC-coupled to the MAC through a 0.1µF capacitor when operating in SGMII mode. TX_D0 28 I, PD TRANSMIT DATA Bit 0: This signal carries data from the MAC to the PHY in RGMII mode. This pin is synchronous to the transmit clock GTX_CLK. GTX_CLK 29 I, PD RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the MAC layer to the PHY. Nominal frequency is 125MHz. RX_CLK 32 O RGMII RECEIVE CLOCK: Provides the recovered receive clocks for different modes of operation: 2.5MHz in 10Mbps mode. 25MHz in 100Mbps mode. 125MHz in 1000Mbps mode. SGMII_COP 33 S, O Differential SGMII Clock Output: This signal is a continuous 625MHz clock signal driven by the PHY in SGMII mode. This pin can be AC-coupled to the MAC through a 0.1µF capacitor when operating in SGMII mode. RX_D0 33 S, O, PD RECEIVE DATA Bit 0: This signal carries data from the PHY to the MAC in RGMII mode. This pin is synchronous to the receive clock RX_CLK. SGMII_CON 34 S, O, PD Differential SGMII Clock Output: This signal is a continuous 625MHz clock signal driven by the MAC in SGMII mode. This pin can be AC-coupled to the MAC through a 0.1µF capacitor when operating in SGMII mode. RX_D1 34 O, PD RECEIVE DATA Bit 1: This signal carries data from the PHY to the MAC in RGMII mode. This pin is synchronous to the receive clock RX_CLK. SGMII_SOP 35 S, O, PD Differential SGMII Data Output: This signal carries data from the PHY to the MAC in SGMII mode. This pin is synchronous to the differential SGMII clock output. This pin can be AC-coupled to the MAC through a 0.1µF capacitor when operating in SGMII mode. RX_D2 35 S, O, PD RECEIVE DATA Bit 2: This signal carries data from the PHY to the MAC in RGMII mode. This pin is synchronous to the receive clock RX_CLK. SGMII_SON 36 S, O, PD Differential SGMII Data Output: This signal carries data from the PHY to the MAC in SGMII mode. This pin is synchronous to the differential SGMII clock output. This pin can be AC-coupled to the MAC through a 0.1µF capacitor when operating in SGMII mode. RX_D3 36 O, PD RECEIVE DATA Bit 3: This signal carries data from the PHY to the MAC in RGMII mode. This pin is synchronous to the receive clock RX_CLK. DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 www.ti.com 4 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E |
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