DP83867CS datasheet(5/129 Pages) TI2

5 / 129 page

Table 5-1. Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME

NO.

TX_CTRL

I, PD

TRANSMIT CONTROL: In RGMII mode, This pin combines the transmit enable

and the transmit error signals of GMII mode using both clock edges.

RX_CTRL

S, O, PD

RECEIVE CONTROL: In RGMII mode, the receive data available and receive

error are combined (RXDV_ER) using both rising and falling edges of the

receive clock (RX_CLK).

GENERAL-PURPOSE I/O

GPIO_0

S, O, PD

General-Purpose I/O: This signal provides a multi-function configurable I/O.

Refer to the GPIO_MUX_CTRL register for details.

GPIO_1

S, O, PD

General-Purpose I/O: This signal provides a multi-function configurable I/O.

Refer to the GPIO_MUX_CTRL register for details.

MANAGEMENT INTERFACE

MDC

I, PD

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial

management input and output data. This clock can be asynchronous to the

MAC transmit and receive clocks. The maximum clock rate is 25MHz and no

minimum.

MDIO

I/O

MANAGEMENT DATA I/O: Bidirectional management instruction and data

signal that can be sourced by the management station or the PHY. This pin

requires pullup resistor. The IEEE specified resistor value is 1.5kΩ, but a 2.2kΩ

is acceptable.

INT / PWDN

I/O, PU

INTERRUPT / POWER DOWN:

The default function of this pin is POWER DOWN.

POWER DOWN: This is an Active Low Input. Asserting this signal low

enables the power-down mode of operation. In this mode, the device powers

down and consume minimum power. Register access is available through the

Management Interface to configure and power up the device.

INTERRUPT: When operating the pin as an interrupt, this pin uses an open-

drain architecture. TI recommends using an external 2.2kΩ resistor connected

to the VDDIO supply.

RESET

RESET_N

I, PU

RESET: The active low RESET initializes or reinitializes the DP83867. All

internal registers re-initialize to default state upon assertion of RESET. The

RESET input must be held low for a minimum of 1µs.

CLOCK INTERFACE

CRYSTAL/OSCILLATOR INPUT: 25MHz oscillator or crystal input (50ppm)

CRYSTAL OUTPUT: Second terminal for 25MHz crystal. Must be left floating if

a clock oscillator is used.

CLK_OUT

CLOCK OUTPUT: Output clock

JTAG INTERFACE

JTAG_CLK

I, PU

JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all

test logic input and output controlled by the testing entity. Supports a maximum

clock frequency of 2.5MHz.

JTAG_TDO

JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most

recent test results are scanned out of the device through TDO.

JTAG_TMS

I, PU

JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS

pin sequences the Tap Controller (16-state FSM) to select the desired test

instruction. TI recommends applying 3 clock cycles with JTAG_TMS high to

reset the JTAG.

JTAG_TDI

I, PU

JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is

scanned into the device through TDI.

LED INTERFACE

LED_2

S, I/O, PD

LED_2: By default, this pin indicates receive or transmit activity. Additional

functionality is configurable through LEDCR1[11:8] register bits.

LED_1

S, I/O, PD

LED_1: By default, this pin indicates that 1000BASE-T link is established.

Additional functionality is configurable through LEDCR1[7:4] register bits.

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DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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