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DP83867CS 数据表(PDF) 65 Page - Texas Instruments |
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DP83867CS 数据表(HTML) 65 Page - Texas Instruments |
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65 / 129 page  7.6.18 Configuration Register 2 (CFG2) Table 7-28. Configuration Register 2 (CFG2), Address 0x0014 BIT BIT NAME DEFAULT DESCRIPTION 15:14 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 13 INTERRUPT_POLARITY 1, RW Configure Interrupt Polarity: 1 = Interrupt pin is active low. 0 = Interrupt pin is active high. 12 RESERVED 0, RO RESERVED 11:10 SPEED_OPT_ATTEMPT_CNT 10, RW Speed Optimization Attempt Count: Selects the number of 1000BASE-T link establishment attempt failures prior to performing Speed Optimization. 11 = 8 10 = 4 01 = 2 00 = 1 9 SPEED_OPT_EN RGZ: 0, RW Speed Optimization Enable: 1 = Enable Speed Optimization. 0 = Disable Speed Optimization. PAP: Strap, RW 8 SPEED_OPT_ENHANCED_EN 1, RW Speed Optimization Enhanced Mode Enable: In enhanced mode, speed is optimized if energy is not detected in channels C and D. 1 = Enable Speed Optimization enhanced mode. 0 = Disable Speed Optimization enhanced mode. 7 SGMII_AUTONEG_EN 1, RW SGMII Auto-Negotiation Enable: 1 = Enable SGMII Auto-Negotaition. 0 = Disable SGMII Auto-Negotaition. 6 SPEED_OPT_10M_EN 1, RW Enable Speed Optimization to 10BASE-Te: 1 = Enable speed optimization to 10BASE-Te if link establishment fails in 1000BASE-T and 100BASE-TX . 0 = Disable speed optimization to 10BASE-Te. 5:0 RESERVED 0 0111, RO RESERVED 7.6.19 Receiver Error Counter Register (RECR) Table 7-29. Receiver Error Counter Register (RECR), Address 0x0015 BIT BIT NAME DEFAULT DESCRIPTION 15:0 RXERCNT[15:0] 0, RO, WSC RX_ER Counter: Receive error counter. This register saturates at the maximum value of 0xFFFF. The counter is cleared by dummy write to this register. www.ti.com DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: DP83867CS DP83867IS DP83867E |
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