DP83867CS datasheet(82/129 Pages) TI2

82 / 129 page

7.6.42 BIST Control and Status Register 3 (BICSR3)

Table 7-52. BIST Control and Status Register 3 (BICSR3), Address 0x007B

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PKT_LEN_PRBS

0x05DC, RW

Length of the generated BIST packets. The value of this register

defines the size (in bytes) of every packet that is generated by the

BIST. Default value is 0x05DC, which is equal to 1500 bytes.

Each packet is appended with 13 nibbles of 0x5 and then 0xD5

(SFD).

7.6.43 BIST Control and Status Register 4 (BICSR4)

Table 7-53. BIST Control and Status Register 4 (BICSR4), Address 0x007C

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

RESERVED

0x00, RO

RESERVED

7:0

IPG_LEN

0x7D, RW

Inter Packet Gap (IPG) Length defines the size of the gap (in bytes)

between any 2 successive packets generated by the BIST. Default

value is 0x7D (equal to 500 bytes). An increment in this fields value

corresponds to an addition of 4 bytes to the IPG Length.

7.6.44 Configuration for Receiver's Equalizer (CRE)

Table 7-54. Configuration for Receiver's Equalizer (CRE), Address 0x008A

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

CONFIG_REC_EQ

0x0000, RW

Configuration for receiver's equalizer. Value 0x010F can further

improve the immunity margins during EMC testing.

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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