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DP83867CS 数据表(PDF) 49 Page - Texas Instruments |
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DP83867CS 数据表(HTML) 49 Page - Texas Instruments |
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49 / 129 page  7.6.5 Auto-Negotiation Advertisement Register (ANAR) This register contains the advertised abilities of this device as the settings are transmitted to the link partner during Auto-Negotiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in the Basic Mode Status Register (address 01h) Auto-Negotiation Complete bit, BMSR[5]) can be followed by a renegotiation. This verifies that the new values are properly used in the Auto-Negotiation. Table 7-14. Auto-Negotiation Advertisement Register (ANAR), Address 0x0004 BIT BIT NAME DEFAULT DESCRIPTION 15 NP 0, RW Next Page Indication: 0 = Next Page Transfer not desired. 1 = Next Page Transfer desired. 14 RESERVED 0, RO/P RESERVED by IEEE: Writes ignored, Read as 0. 13 RF 0, RW Remote Fault: 1 = Advertises that this device has detected a Remote Fault. 0 = No Remote Fault detected. 12 RESERVED 0, RW RESERVED for Future IEEE use: Write as 0, Read as 0 11 ASM_DIR 0, RW Asymmetric PAUSE Support for Full Duplex Links: The ASM_DIR bit indicates that asymmetric PAUSE is supported. Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12]. 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of 802.3u. 0 = No MAC based full duplex flow control. 10 PAUSE 0, RW PAUSE Support for Full Duplex Links: The PAUSE bit indicates that the device is capable of providing the symmetric PAUSE functions as defined in Annex 31B. Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12]. 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of 802.3u. 0 = No MAC based full duplex flow control. 9 T4 0, RO/P 100BASE-T4 Support: 1 = 100BASE-T4 is supported by the local device. 0 = 100BASE-T4 not supported. 8 TX_FD Strap, RW 100BASE-TX Full Duplex Support: 1 = 100BASE-TX Full Duplex is supported by the local device. 0 = 100BASE-TX Full Duplex not supported. 7 TX_HD Strap, RW 100BASE-TX Half Support: 1 = 100BASE-TX is supported by the local device. 0 = 100BASE-TX not supported. 6 Te_FD Strap, RW 10BASE-Te Full Duplex Support: 1 = 10BASE-Te Full Duplex is supported by the local device. 0 = 10BASE-Te Full Duplex not supported. www.ti.com DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: DP83867CS DP83867IS DP83867E |
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