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DP83867CS 数据表(PDF) 83 Page - Texas Instruments |
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DP83867CS 数据表(HTML) 83 Page - Texas Instruments |
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83 / 129 page  7.6.45 RGMII Delay Control Register (RGMIIDCTL) This register provides access to the RGMII delay controls. Table 7-55. RGMII Delay Control Register (RGMIIDCTL), Address 0x0086 BIT BIT NAME DEFAULT DESCRIPTION 15:8 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 7:4 RGMII_TX_DELAY_CTRL Strap, RW RGMII Transmit Clock Delay: 1111: 4.00ns 1110: 3.75ns 1101: 3.50ns 1100: 3.25ns 1011: 3.00ns 1010: 2.75ns 1001: 2.50ns 1000: 2.25ns 0111: 2.00ns 0110: 1.75ns 0101: 1.50ns 0100: 1.25ns 0011: 1.00ns 0010: 0.75ns 0001: 0.50ns 0000: 0.25ns 3:0 RGMII_RX_DELAY_CTRL Strap, RW RGMII Receive Clock Delay: 1111: 4.00ns 1110: 3.75ns 1101: 3.50ns 1100: 3.25ns 1011: 3.00ns 1010: 2.75ns 1001: 2.50ns 1000: 2.25ns 0111: 2.00ns 0110: 1.75ns 0101: 1.50ns 0100: 1.25ns 0011: 1.00ns 0010: 0.75ns 0001: 0.50ns 0000: 0.25ns 7.6.46 ANA_LD_TXG_FINE_GAINSEL_AB (ALTFGAB) Table 7-56. ANA_LD_TXG_FINE_GAINSEL_AB (ALTFGAB), Address 0x00A0 BIT BIT NAME DEFAULT DESCRIPTION 15:12 Reserved 0000,RO RESERVED 11:8 TXG_GAINSEL_FINE_B trim,RW Gain control channel B. For details, see bits [3:0] 7:4 Reserved 0000,RO RESERVED 3:0 TXG_GAINSEL_FINE_A trim,RW Gain control channel A. Default value is set by trim. Possible values: x0000 = -16% change in gain x0001 = -14% change in gain x1000 = No change in gain x1001 = +2% change in gain x1111 = +14% change in gain www.ti.com DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 83 Product Folder Links: DP83867CS DP83867IS DP83867E |
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