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DP83867CS 数据表(PDF) 73 Page - Texas Instruments |
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DP83867CS 数据表(HTML) 73 Page - Texas Instruments |
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73 / 129 page  7.6.26 Control Register (CTRL) Table 7-36. Control Register (CTRL), Address 0x001F BIT BIT NAME DEFAULT DESCRIPTION 15 SW_RESET 0, RW, SC Software Reset: 1 = Perform a full reset, including registers. 0 = Normal operation. 14 SW_RESTART 0, RW, SC Software Restart: 1 = Perform a full reset, not including registers. . 0 = Normal operation. 13:0 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 7.6.27 Testmode Channel Control (TMCH_CTRL) Table 7-37. Testmode Channel Control (TMCH_CTRL), Address 0x0025 BIT BIT NAME DEFAULT DESCRIPTION 15:8 RESERVED 0x04 RESERVED 7:5 TM_CH_SEL 0x0 Test mode Channel Select. If bit 7 is set then Test mode is driven on all 4 channels. If bit 7 is cleared then test modes are driven according to bits 6:5 as follows: 00: Channel A 01: Channel B 10: Channel C 11: Channel D 4:0 RESERVED 0x00 RESERVED www.ti.com DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: DP83867CS DP83867IS DP83867E |
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