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DP83867CS 数据表(PDF) 80 Page - Texas Instruments |
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DP83867CS 数据表(HTML) 80 Page - Texas Instruments |
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80 / 129 page  7.6.38 Strap Configuration Status Register 1 (STRAP_STS1) Strap Configuration Status Register 1 (STRAP_STS1), Address 0x006E Table 7-48. Strap Configuration Status Register 1 (STRAP_STS1), Address 0x006E BIT BIT NAME DEFAULT DESCRIPTION 15 STRAP_MIRROR_EN Strap, RO Mirror Enable Strap: 1 = Port mirroring strapped to enable. 0 = Port mirroring strapped to disable. 14 STRAP_LINK_DOWNSHIFT_EN Strap, RO Link Downshift Enable Strap: 1 = Link Downshift strapped to enable. 0 = Link Downshift strapped to disable. 13 STRAP_CLK_OUT_DIS Strap, RO Clock Output Disable Strap: 1 = Clock output strapped to disable. 0 = Clock output strapped to enable. 12 STRAP_RGMII_DIS Strap, RO RGMII Disable Strap: 1 = RGMII strapped to disable. 0 = RGMII strapped to enable. 11 STRAP_SGMII_EN Strap, RO SGMII Enable Strap: 1 = SGMII strapped to enable. 0 = SGMII strapped to disable. 10 STRAP_AMDIX_DIS Strap, RO Auto-MDIX Disable Strap: 1 = Auto-MDIX strapped to disable. 0 = Auto-MDIX strapped to enable. 9 STRAP_FORCE_MDI_X Strap, RO Force MDI/X Strap: 1 = Force MDIX strapped to enable. 0 = Force MDI strapped to enable. 8 STRAP_HD_EN Strap, RO Half Duplex Enable Strap: 1 = Half Duplex strapped to enable. 0 = Full Duplex strapped to enable. 7 STRAP_ANEG_DIS Strap, RO Auto-Negotiation Disable Strap: 1 = Auto-Negotiation strapped to disable. 0 = Auto-Negotiation strapped to enable. 6 RESERVED 0, RO RESERVED 5 STRAP_ANEG_SEL Strap, RO ANEG_SEL value from strap. See Auto-Negotiation Select Strap Details table. 4 RESERVED 0, RO RESERVED 3:0 STRAP_PHY_ADD Strap, RO PHY Address Strap: PHY address value from straps. DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 www.ti.com 80 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E |
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