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DP83867CS 数据表(PDF) 12 Page - Texas Instruments |
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DP83867CS 数据表(HTML) 12 Page - Texas Instruments |
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12 / 129 page  6.9 SGMII Timing See Figure 6-4. PARAMETER TEST CONDITIONS (3) MIN NOM MAX UNIT T1 SGMII Clock Output Duty Cycle 48% 52% T2 Setup time See (1) 100 ps T3 Clock to Data relationship from either edges of the clock to valid data See (2) 250 550 ps TR VOD fall time 20% - 80% 100 200 ps TF VOD rise time 20% - 80% 100 200 ps Thold Hold time See (1) 100 ps TTXLAT SGMII to MDI Latency See (4) 201 ns TRXLAT MDI to SGMII Latency See (4) 289 ns (1) Setup and hold time are measured at 50% of the transition. (2) T3 is measured at 0V differential. (3) Specified by production test, characterization, or design. (4) Operating in 1000Base-T 6.10 RGMII Timing See Figure 6-5 and .Figure 6-6 PARAMETER TEST CONDITIONS (5) MIN NOM MAX UNIT TskewT Data to Clock output Skew (at Transmitter) See (1) –500 0 500 ps TskewR Data to Clock input Skew (at Receiver) See (1) 1 1.8 2.6 ns TsetupT Data to Clock output Setup (at Transmitter – internal delay) See (4) 1.2 2 ns TholdT Clock to Data output Hold (at Transmitter – internal delay) See (4) 1.2 2 ns TsetupR Data to Clock input Setup (at Reciever – internal delay) See (4) 1 2 ns TholdR Clock to Data input Hold (at Receiver – internal delay) See (4) 1 2 ns Tcyc Clock Cycle Duration See (2) 7.2 8 8.8 ns Duty_G Duty Cycle for Gigabit See (3) (7) 45 50 55% Duty_T Duty Cycle for 10/100T See (3) (7) 40 50 60% TR Rise Time (20% to 80%) 0.75 ns TF Fall Time (20% to 80%) 0.75 ns TTXLAT RGMII to MDI Latency See (6) 88 ns TRXLAT MDI to RGMII Latency See (6) 288 ns (1) When operating without RGMII internal delay, the PCB design requires clocks to be routed such that an additional trace delay of greater than 1.5ns is added to the associated clock signal. (2) For 10Mbps and 100Mbps, Tcyc scales to 400ns ± 40ns and 40ns ± 4ns. (3) Duty cycle can be stretched or shrunk during speed changes or while transitioning to a received packet’s clock domain as long as minimum duty cycle is not violated and stretching occurs for no more that three Tcyc of the lowest speed transitioned between. (4) Device can operate with or without internal delay. (5) Specified by production test, characterization, or design. (6) Operating in 1000Base-T . (7) Duty cycle values are defined in percentages of the nominal clock speed. For example, the minimum Gigabit RGMII clock pulse duration is 45 % of 8ns. DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 www.ti.com 12 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E |
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