DP83867CS datasheet(64/129 Pages) TI2

64 / 129 page

Table 7-27. Interrupt Status Register (ISR), Address 0x0013 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

SPEED_OPT_EVENT_INT

0, RO, LH, COR Speed Optimization Event Interrupt:

1 = Speed Optimization Event Interrupt is pending and is cleared by

the current read.

0 = No Speed Optimization Event Interrupt is pending.

SLEEP_MODE_CHNG_INT

0, RO, LH, COR Sleep Mode Change Interrupt:

1 = Sleep Mode Change Interrupt is pending and is cleared by the

current read.

0 = No Sleep Mode Change Interrupt is pending.

WOL_INT

0, RO, LH, COR Wake-on-LAN Interrupt:

1 = Wake-on-LAN Interrupt is pending.

0 = No Wake-on-LAN Interrupt is pending.

XGMII_ERR_INT 1

0, RO, LH, COR xGMII Error Interrupt:

1 = xGMII Error Interrupt is pending and is cleared by the current

read.

0 = No xGMII Error Interrupt is pending.

POLARITY_CHNG_INT

0, RO, LH, COR Polarity Change Interrupt:

1 = Polarity Change interrupt is pending and is cleared by the current

read.

0 = No Polarity Change interrupt is pending.

JABBER_INT

0, RO, LH, COR Jabber Interrupt:

1 = Jabber interrupt is pending and is cleared by the current read.

0 = No Jabber interrupt is pending.

1 xGMII: RGMII or SGMII

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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